CHIP Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: `0fc384d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.779m	2.610ms	1	1	100.00
		chip_sw_example_rom	1.324m	2.514ms	1	1	100.00
		chip_sw_example_manufacturer	1.873m	2.190ms	1	1	100.00
		chip_sw_example_concurrency	2.243m	2.392ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.560m	4.343ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.079m	5.297ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.000m	7.468ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.183h	35.542ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	42.010s	2.238ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.183h	35.542ms	1	1	100.00
		chip_csr_rw	6.079m	5.297ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.650s	207.027us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.762m	4.606ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.762m	4.606ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.762m	4.606ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.681m	4.261ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.681m	4.261ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.832m	4.320ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.053m	4.352ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.103m	3.903ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.704m	3.454ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.785m	13.337ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.169m	4.856ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.745m	4.565ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.745m	4.565ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.995m	3.155ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.976m	2.993ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.232m	2.711ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.312m	4.180ms	1	1	100.00
		chip_tap_straps_testunlock0	2.349m	3.144ms	1	1	100.00
		chip_tap_straps_rma	6.643m	7.121ms	1	1	100.00
		chip_tap_straps_prod	1.843m	2.706ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.371m	2.448ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	15.481m	9.788ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.136m	5.462ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.136m	5.462ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.404m	7.764ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	36.555m	20.590ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.186m	4.108ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.951m	5.695ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.497m	18.862ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.857m	2.341ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.243m	7.092ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.289m	2.488ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.394m	11.240ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.340m	2.832ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.487m	3.828ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.523m	2.525ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.944m	3.098ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.256m	5.480ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.065m	5.207ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.579m	3.425ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.065m	5.207ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.569m	2.814ms	1	1	100.00
		chip_sw_aes_smoketest	2.593m	2.878ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.699m	3.467ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.846m	2.553ms	1	1	100.00
		chip_sw_csrng_smoketest	1.566m	2.222ms	1	1	100.00
		chip_sw_entropy_src_smoketest	15.068m	7.415ms	1	1	100.00
		chip_sw_gpio_smoketest	3.500m	2.938ms	1	1	100.00
		chip_sw_hmac_smoketest	3.900m	3.299ms	1	1	100.00
		chip_sw_kmac_smoketest	2.941m	3.399ms	1	1	100.00
		chip_sw_otbn_smoketest	13.998m	7.643ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.182m	6.238ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.652m	6.177ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.741m	3.026ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.516m	3.437ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.040m	2.791ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.669m	2.884ms	1	1	100.00
		chip_sw_uart_smoketest	3.066m	3.500ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.752m	3.408ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.567m	4.066ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.178h	61.590ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	43.436m	14.716ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.680m	7.008ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.423m	2.472ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.391m	2.627ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.009h	54.107ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.045h	55.561ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	52.480s	2.092ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	52.480s	2.092ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.183h	35.542ms	1	1	100.00
		chip_same_csr_outstanding	48.233m	30.855ms	1	1	100.00
		chip_csr_hw_reset	2.560m	4.343ms	1	1	100.00
		chip_csr_rw	6.079m	5.297ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.183h	35.542ms	1	1	100.00
		chip_same_csr_outstanding	48.233m	30.855ms	1	1	100.00
		chip_csr_hw_reset	2.560m	4.343ms	1	1	100.00
		chip_csr_rw	6.079m	5.297ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	27.040s	487.963us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.400s	55.043us	1	1	100.00
		xbar_smoke_large_delays	41.330s	6.608ms	1	1	100.00
		xbar_smoke_slow_rsp	35.190s	3.864ms	1	1	100.00
		xbar_random_zero_delays	12.340s	157.339us	1	1	100.00
		xbar_random_large_delays	32.620s	5.226ms	1	1	100.00
		xbar_random_slow_rsp	34.410s	3.895ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	11.220s	120.191us	1	1	100.00
		xbar_error_and_unmapped_addr	22.750s	840.214us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	9.530s	136.448us	1	1	100.00
		xbar_error_and_unmapped_addr	22.750s	840.214us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.051m	2.797ms	1	1	100.00
		xbar_access_same_device_slow_rsp	1.600m	10.517ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	6.420s	40.537us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.205m	2.745ms	1	1	100.00
		xbar_stress_all_with_error	29.370s	1.332ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.600m	1.990ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.290m	3.880ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	43.436m	14.716ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	38.470m	32.068ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.367m	18.663ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.011m	13.330ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.620m	15.670ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.895m	15.530ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.293m	16.370ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.195m	14.760ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.090s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.090s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.850s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.150s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.150s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.150s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.560s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.710s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	19.620s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.500s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.810s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.700s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.030s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.790s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	22.280s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.560s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.620s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.350s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.890s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.140s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.240s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.280s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.610s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.690s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.050s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.737m	11.136ms	1	1	100.00
		rom_e2e_asm_init_dev	40.779m	15.860ms	1	1	100.00
		rom_e2e_asm_init_prod	43.600m	15.510ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.438m	14.855ms	1	1	100.00
		rom_e2e_asm_init_rma	42.148m	16.180ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	41.036m	15.555ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.402m	16.412ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.673m	14.513ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.339m	15.960ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.182m	34.716ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.182m	34.716ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.745m	3.211ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.857m	2.341ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.919m	2.905ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.661m	2.642ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	27.737m	12.773ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.566m	2.532ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.507m	4.726ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.776m	5.660ms	1	1	100.00
		chip_plic_all_irqs_10	3.854m	3.707ms	1	1	100.00
		chip_plic_all_irqs_20	5.525m	3.685ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.584m	2.988ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.151m	12.220ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.065m	3.946ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.038m	2.664ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.088m	8.017ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.438m	6.222ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.973m	7.810ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.417h	256.233ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.497m	4.296ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.182m	6.238ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.497m	4.296ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.215m	7.687ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.215m	7.687ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.328m	8.086ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.870m	4.608ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.450m	6.095ms	1	1	100.00
		chip_sw_aes_idle	1.661m	2.642ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.776m	2.745ms	1	1	100.00
		chip_sw_kmac_idle	2.080m	2.502ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.296m	5.299ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	2.819m	4.175ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.849m	4.469ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.433m	3.580ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	15.691m	11.135ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.636m	3.493ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.074m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.805m	3.717ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.740m	4.187ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.502m	4.147ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.205m	4.827ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.404m	7.764ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.243m	11.668ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.805m	3.717ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.740m	4.187ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.186m	4.108ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.951m	5.695ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.497m	18.862ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.857m	2.341ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.243m	7.092ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.289m	2.488ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.394m	11.240ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.340m	2.832ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.487m	3.828ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.523m	2.525ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.018m	2.544ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.009m	4.607ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.512m	6.597ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.320m	24.813ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.571m	3.150ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.708m	3.130ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	15.215m	9.586ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.457m	3.722ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.487m	4.831ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.218m	25.114ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	51.632m	30.172ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.404m	7.764ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.382m	4.871ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.276m	3.632ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	19.088m	8.017ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.515m	6.758ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	5.234m	5.323ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.816m	5.594ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.628m	2.863ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.118h	26.181ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.181m	3.097ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.710m	6.527ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.181m	3.097ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.515m	6.758ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.478m	3.251ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	23.239m	25.476ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.175m	5.389ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.951m	5.695ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.013m	4.189ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.186m	4.108ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.713m	43.953ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	23.239m	25.476ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.151m	3.165ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	14.568m	6.858ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.362m	4.514ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.713m	43.953ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.362m	4.514ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.362m	4.514ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.362m	4.514ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.362m	4.514ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.522m	10.954ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.678m	5.071ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.152m	5.379ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.152m	5.379ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.592m	2.969ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.289m	2.488ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.776m	2.745ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.006m	3.015ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.262m	4.350ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.092m	4.769ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.470m	4.697ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.845m	4.948ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.173m	3.352ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	14.568m	6.858ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.394m	11.240ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.249m	10.828ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	27.737m	12.773ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.383m	12.740ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.725m	2.578ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.955m	3.594ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.340m	2.832ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	14.568m	6.858ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.589m	2.181ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.538m	7.206ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.080m	2.502ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.507m	4.726ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.312m	4.180ms	1	1	100.00
		chip_tap_straps_rma	6.643m	7.121ms	1	1	100.00
		chip_tap_straps_prod	1.843m	2.706ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.651m	2.995ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.043m	7.898ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.362m	4.514ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.713m	43.953ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.162m	2.899ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.089m	5.735ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.006m	8.078ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.637m	6.822ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.568m	6.858ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.881m	9.463ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.558m	8.315ms	1	1	100.00
		chip_prim_tl_access	4.522m	10.954ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.243m	11.668ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.636m	3.493ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.074m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.805m	3.717ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.740m	4.187ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.502m	4.147ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.205m	4.827ms	1	1	100.00
		chip_tap_straps_dev	3.312m	4.180ms	1	1	100.00
		chip_tap_straps_rma	6.643m	7.121ms	1	1	100.00
		chip_tap_straps_prod	1.843m	2.706ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.216m	3.241ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.731m	2.934ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.318m	3.334ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.768m	3.684ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.278m	3.247ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.163m	29.114ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.216m	3.241ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.063h	49.043ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.075h	50.598ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.667m	11.918ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.434m	46.702ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.163m	29.114ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.317m	2.805ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	56.350s	2.104ms	1	1	100.00
		rom_volatile_raw_unlock	1.047m	1.966ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.319m	17.287ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.497m	18.862ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.450m	6.095ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.450m	6.095ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.450m	6.095ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.626m	3.197ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	23.239m	25.476ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.626m	3.197ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.568m	6.858ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.494m	4.197ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.935m	2.630ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	23.239m	25.476ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.626m	3.197ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.568m	6.858ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.494m	4.197ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.935m	2.630ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.471m	5.012ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.651m	2.995ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.162m	2.899ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.089m	5.735ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.006m	8.078ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.637m	6.822ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.693m	6.796ms	1	1	100.00
		chip_prim_tl_access	4.522m	10.954ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.522m	10.954ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.422m	8.876ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.115m	10.088ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.202m	23.795ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.784m	7.692ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.983m	9.234ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.948m	7.030ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.870m	24.793ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.669m	17.010ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.215m	7.687ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.597m	11.179ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.486m	5.200ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.115m	10.088ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.861m	5.051ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.049m	37.285ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.718m	5.764ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.406m	4.630ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.390m	27.297ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.583m	8.236ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.782m	11.180ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.968m	30.449ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.630m	2.700ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.881m	9.463ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.881m	9.463ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.782m	11.180ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.390m	27.297ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.486m	5.200ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.182m	6.238ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.342m	4.412ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.789m	4.627ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.439m	4.672ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.151m	12.220ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.188m	2.984ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.438m	6.222ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.891m	4.755ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.300m	4.624ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.414m	3.511ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.935m	2.630ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.789m	4.627ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.789m	4.627ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	15.544m	12.637ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.956m	13.269ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.342m	4.412ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.708m	4.572ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.180m	6.197ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.643m	7.121ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.216m	3.241ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.776m	5.660ms	1	1	100.00
		chip_plic_all_irqs_10	3.854m	3.707ms	1	1	100.00
		chip_plic_all_irqs_20	5.525m	3.685ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.615m	2.926ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.215m	2.933ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	43.436m	14.716ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.391m	7.060ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.099m	3.327ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.361m	3.249ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.594m	2.126ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.494m	4.197ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.487m	3.828ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.615m	8.233ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.243m	7.074ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.558m	8.315ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.136m	5.462ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.583m	8.236ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.088m	23.323ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.665m	2.731ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.635m	3.628ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.266m	4.310ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.088m	23.323ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.088m	23.323ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.903m	11.652ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.903m	11.652ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.406m	5.382ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.182m	34.716ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.989m	3.111ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.473m	3.221ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.729m	3.812ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.889m	4.005ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.044m	8.858ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.493h	31.483ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.490m	11.903ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.925m	3.437ms	1	1	100.00
V2		TOTAL			235	275	85.45
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.526m	3.427ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.654m	2.665ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.540h	71.691ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.367m	4.712ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.467m	12.015ms	1	1	100.00
		rom_e2e_jtag_debug_dev	10.192m	7.121ms	0	1	0.00
		rom_e2e_jtag_debug_rma	18.095m	11.721ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.090m	4.606ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.865m	3.353ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.956m	5.275ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.494s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.225m	5.061ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.133m	2.635ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	7.909m	4.077ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	21.294m	9.272ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.698m	2.531ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.634m	5.341ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.349m	2.338ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.875m	5.791ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.986m	5.748ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.292m	3.756ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.782m	11.180ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.467m	12.015ms	1	1	100.00
		rom_e2e_jtag_debug_dev	10.192m	7.121ms	0	1	0.00
		rom_e2e_jtag_debug_rma	18.095m	11.721ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.515m	4.963ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.784m	4.285ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.594h	38.677ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.594h	38.677ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.473m	4.178ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.681m	4.261ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	55.085m	18.912ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.873m	3.261ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.208m	4.460ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	31.546m	22.122ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.085m	3.245ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.599m	3.484ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.306m	3.156ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.326s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.820m	3.179ms	1	1	100.00
		TOTAL			279	326	85.58

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.42135004577426042730284091739076370114545292551121988252103600893796718219857
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.76584580579451817797265510380220748359296069624948654031119371151888420696632
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.15164786705858856306709272533266413198973462191991867642589821876026966564795
    Line 538, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.99636468495982638324066087536059776645591478441669988729831229667990585262949
    Line 532, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.76363090747594185315719233537918716630665901832714677615720661693898905244909
    Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.41506749877540050339723935359645065459271812236273827737119903960852554742465
    Line 574, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.16463363835388905198857053648046122202019917368742431198351554645351539864624
    Line 553, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1639651015368306694257459485214246436545217629823352971488262366219761897071
    Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.107760911753001696575496113725366309834743454365757811365003669730161826978594
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.22532827565935049592112544633136367136152224136888555992366741910073044663690
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.14682811367600163353460001069206534810820945814426772859785716746732725553114
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.74153044793490133091406313975693951973511165636066673460829980783748474887840
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.109986796036790970763724149916992030518853058337837970454552068752051279184107
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.106060173302594230835320183768991298020442314679905689448137174782676283969547
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.210s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.94351674932833186468943637681928807116924552409570210376882996238553714036259
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.157s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.35484291184807440298413490701774343391522075553926077505067558372738073437014
    Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.6235118532292722899958602916746675214738965530735956249310768452909782789365
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.87533863299445740085383543514715685166359027927227017404174179089698923976187
    Line 556, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.85467978058446264733953606645660499831573567639111436861964103231817908365839
    Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.89621935518194418089550905389027541166029489765346252076499635174461914085490
    Line 568, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3155.380000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3155.380000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.60047043618614818321391078834782446389914028639157309993795653929628453247719
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3327.464192 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3327.464192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.72233982707401377848584521357929128980601261203848553902075936503523050422154
    Line 424, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6821.851720 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6821.851720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.110222202129219463421715594851151090801782894682713736242659619734423365449227
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 22121.570359 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 22121.570359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@83562) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.24764104300049311397070784916529259285964253714943401404898275354225153563610
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4626.582675 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@83562) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4626.582675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.17904720124191934351488835030242845308169744540448331256287954131018707322982
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11652.053072 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11652.053072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.51976000726666657036905192153434574509947550332481357928910872573916213442709
    Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34716.473995 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34716.473995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.77041280337507062585755310396441646803119721014738060379477622845610320470181
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2531.705563 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2531.705563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.100959426126986636834847018572379717756668955833262001595179164769624031685274
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2664.385602 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2664.385602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.115496394526090098385773028341218858737362660236248873421283892682610925681510
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.72548368165826577466299521960421450412691738237450380047409479310190095178666
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3015.065600 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3015.065600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35142) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.51114494561971420213350202555262597692491732944385335330554489369479346276421
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2092.034217 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35142) { a_addr: 'h105fc  a_data: 'h3c200869  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1ae99  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2092.034217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.20902717389452463107958081596304594223298925916563457222839677667521017868770
    Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 3240.552978 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10670 read out mismatch
  UVM_INFO @ 3240.552978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.64067783503207372281605823068204121920064395950154703572929267911390007199390
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2664.601870 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2664.601870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.98748342748494683079990035903977708320590630935177434770464557305066503527053
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2471.714500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2471.714500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.103951799123921734948562158146846046173381595949294881090969937496097569836584
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2626.860000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2626.860000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.60403972263474293685894344061589587960353360913947906795776773646072387711826
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20590.374065 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20590.374065 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.108371678902711937583114747908501283770386129574100261363175325270686921716762
    Line 451, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4712.324546 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4712.324546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.18284164421083609524669097876471365557731930509249655261003354704896766283619
    Line 512, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.33424140336552384209194744094665651122769877248096857492430850641461519762541
    Line 465, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:259) [chip_sw_rom_e2e_jtag_debug_vseq] Check failed status == * (* [*] vs * [*]) has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.43724656827074514607101784751967470604340163377827862143210735221170174130265
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 7121.293060 us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:259) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_jtag_debug_vseq] Check failed status == 0 (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 7121.293060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32170) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.29291683147543340036319877500012054290146437439191762784420272499817557969252
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2238.115460 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32170) { a_addr: 'h10604  a_data: 'hb7935d51  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h19275  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2238.115460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---