ADC_CTRL Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.390s	5.951ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.620s	967.758us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.010s	581.264us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	18.980s	37.813ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.550s	1.098ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.150s	611.646us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.010s	581.264us	1	1	100.00
		adc_ctrl_csr_aliasing	3.550s	1.098ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.260m	164.919ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	12.162m	485.285ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.682m	169.191ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.403m	332.617ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.562m	184.181ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.476m	619.707ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.899m	545.128ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.630s	1.828ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	4.880s	5.130ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	42.760s	26.444ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	40.350s	89.890ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.881m	334.986ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.740s	323.315us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.880s	320.023us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.520s	491.230us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.520s	491.230us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.620s	967.758us	1	1	100.00
		adc_ctrl_csr_rw	1.010s	581.264us	1	1	100.00
		adc_ctrl_csr_aliasing	3.550s	1.098ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.360s	2.069ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.620s	967.758us	1	1	100.00
		adc_ctrl_csr_rw	1.010s	581.264us	1	1	100.00
		adc_ctrl_csr_aliasing	3.550s	1.098ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.360s	2.069ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.280s	4.609ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.190s	7.889ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.190s	7.889ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.650s	2.449ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.29435007938802277127089374197963308975605561068356956458989704388421496754835
      Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 1828231876 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 1828231876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---