HMAC Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.470s 64.958us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.720s 37.685us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.730s 47.058us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.000s 14.932ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.580s 2.007ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.920s 134.318us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.730s 47.058us 1 1 100.00
hmac_csr_aliasing 4.580s 2.007ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 8.870s 924.010us 1 1 100.00
V2 back_pressure hmac_back_pressure 1.331m 7.056ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.600s 157.227us 1 1 100.00
hmac_test_sha384_vectors 19.260s 262.865us 1 1 100.00
hmac_test_sha512_vectors 6.198m 49.906ms 1 1 100.00
hmac_test_hmac256_vectors 5.080s 622.188us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 335.800us 1 1 100.00
hmac_test_hmac512_vectors 9.010s 270.171us 1 1 100.00
V2 burst_wr hmac_burst_wr 13.660s 367.576us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 34.660s 737.678us 1 1 100.00
V2 error hmac_error 39.340s 1.584ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 14.350s 4.538ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.470s 64.958us 1 1 100.00
hmac_long_msg 8.870s 924.010us 1 1 100.00
hmac_back_pressure 1.331m 7.056ms 1 1 100.00
hmac_datapath_stress 34.660s 737.678us 1 1 100.00
hmac_burst_wr 13.660s 367.576us 1 1 100.00
hmac_stress_all 7.635m 35.904ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.470s 64.958us 1 1 100.00
hmac_long_msg 8.870s 924.010us 1 1 100.00
hmac_back_pressure 1.331m 7.056ms 1 1 100.00
hmac_datapath_stress 34.660s 737.678us 1 1 100.00
hmac_wipe_secret 14.350s 4.538ms 1 1 100.00
hmac_test_sha256_vectors 7.600s 157.227us 1 1 100.00
hmac_test_sha384_vectors 19.260s 262.865us 1 1 100.00
hmac_test_sha512_vectors 6.198m 49.906ms 1 1 100.00
hmac_test_hmac256_vectors 5.080s 622.188us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 335.800us 1 1 100.00
hmac_test_hmac512_vectors 9.010s 270.171us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.470s 64.958us 1 1 100.00
hmac_long_msg 8.870s 924.010us 1 1 100.00
hmac_back_pressure 1.331m 7.056ms 1 1 100.00
hmac_datapath_stress 34.660s 737.678us 1 1 100.00
hmac_burst_wr 13.660s 367.576us 1 1 100.00
hmac_error 39.340s 1.584ms 1 1 100.00
hmac_wipe_secret 14.350s 4.538ms 1 1 100.00
hmac_test_sha256_vectors 7.600s 157.227us 1 1 100.00
hmac_test_sha384_vectors 19.260s 262.865us 1 1 100.00
hmac_test_sha512_vectors 6.198m 49.906ms 1 1 100.00
hmac_test_hmac256_vectors 5.080s 622.188us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 335.800us 1 1 100.00
hmac_test_hmac512_vectors 9.010s 270.171us 1 1 100.00
hmac_stress_all 7.635m 35.904ms 1 1 100.00
V2 stress_all hmac_stress_all 7.635m 35.904ms 1 1 100.00
V2 alert_test hmac_alert_test 0.740s 12.460us 1 1 100.00
V2 intr_test hmac_intr_test 0.630s 16.069us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.180s 4.729ms 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.180s 4.729ms 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.720s 37.685us 1 1 100.00
hmac_csr_rw 0.730s 47.058us 1 1 100.00
hmac_csr_aliasing 4.580s 2.007ms 1 1 100.00
hmac_same_csr_outstanding 2.020s 90.961us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.720s 37.685us 1 1 100.00
hmac_csr_rw 0.730s 47.058us 1 1 100.00
hmac_csr_aliasing 4.580s 2.007ms 1 1 100.00
hmac_same_csr_outstanding 2.020s 90.961us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.170s 157.803us 1 1 100.00
hmac_tl_intg_err 1.570s 372.383us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.570s 372.383us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.470s 64.958us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.700s 917.536us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.073m 18.483ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.860s 23.792us 1 1 100.00
TOTAL 28 28 100.00