I2C Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	22.030s	4.311ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.720s	826.981us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	64.829us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.720s	45.136us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.520s	1.851ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.050s	84.747us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.980s	68.807us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.720s	45.136us	1	1	100.00
		i2c_csr_aliasing	1.050s	84.747us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.350s	20.371us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	3.417m	80.540ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.650s	245.321us	1	1	100.00
V2	host_override	i2c_host_override	0.780s	29.594us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.253m	24.345ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	28.410s	8.339ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.870s	107.836us	1	1	100.00
		i2c_host_fifo_fmt_empty	15.900s	1.736ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.510s	140.073us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.137m	7.924ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	5.840s	531.558us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.300s	113.110us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.300s	944.641us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	46.970s	38.192ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.200s	2.398ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.590s	5.253ms	1	1	100.00
		i2c_target_intr_smoke	6.870s	926.977us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.860s	222.586us	1	1	100.00
		i2c_target_fifo_reset_tx	1.120s	184.679us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.602m	37.651ms	1	1	100.00
		i2c_target_stress_rd	14.590s	5.253ms	1	1	100.00
		i2c_target_intr_stress_wr	12.060s	2.563ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.830s	5.029ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	10.430s	2.642ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.370s	1.631ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.210s	509.778us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.020s	1.604ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.010s	126.699us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.650s	245.321us	1	1	100.00
		i2c_host_perf_precise	36.150s	24.642ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	5.840s	531.558us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.140s	556.182us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.280s	4.164ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.030s	508.128us	1	1	100.00
		i2c_target_nack_txstretch	1.450s	129.986us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.530s	697.206us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.550s	600.818us	1	1	100.00
V2	alert_test	i2c_alert_test	0.770s	43.370us	1	1	100.00
V2	intr_test	i2c_intr_test	0.700s	26.336us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.700s	165.549us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.700s	165.549us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	64.829us	1	1	100.00
		i2c_csr_rw	0.720s	45.136us	1	1	100.00
		i2c_csr_aliasing	1.050s	84.747us	1	1	100.00
		i2c_same_csr_outstanding	1.010s	163.368us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	64.829us	1	1	100.00
		i2c_csr_rw	0.720s	45.136us	1	1	100.00
		i2c_csr_aliasing	1.050s	84.747us	1	1	100.00
		i2c_same_csr_outstanding	1.010s	163.368us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.180s	234.314us	1	1	100.00
		i2c_sec_cm	0.810s	92.700us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.180s	234.314us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.680s	958.145us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.110s	197.840us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	23.660s	897.972us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.16891390319415889946942325773721907538199344901758134017813594205987014669829
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  20371246 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  20371246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.62282033963113985691271512094325807016712682249747222512305040810285154329623
      Line 162, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 80540122393 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @3726811
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.114387914327809712852280385284921037439213421776287147302890289000170940343559
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 944641338 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 944641338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.38702541010110367821415129065654064987598698179536456272627573546211083598612
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 197840370 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 91 [0x5b])
        UVM_INFO @ 197840370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.56148661882084573263513430314602415320441839659991026649642957622565486037940
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 958145405 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 958145405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.106528427020002065329386472937834488657603636331762103446526839432768665576147
      Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 897971567 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 897971567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---