KEYMGR Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.700s 36.202us 1 1 100.00
V1 random keymgr_random 10.960s 1.993ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.880s 49.660us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.220s 113.153us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 5.750s 4.290ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 2.810s 69.601us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.360s 48.098us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.220s 113.153us 1 1 100.00
keymgr_csr_aliasing 2.810s 69.601us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 4.640s 122.678us 1 1 100.00
V2 sideload keymgr_sideload 10.450s 403.232us 1 1 100.00
keymgr_sideload_kmac 1.550s 39.936us 1 1 100.00
keymgr_sideload_aes 2.910s 135.778us 1 1 100.00
keymgr_sideload_otbn 2.340s 159.480us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.130s 60.173us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.730s 78.078us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.000s 81.499us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 5.900s 786.134us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 7.450s 1.215ms 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.460s 139.262us 1 1 100.00
V2 stress_all keymgr_stress_all 23.310s 971.974us 1 1 100.00
V2 intr_test keymgr_intr_test 0.710s 30.339us 1 1 100.00
V2 alert_test keymgr_alert_test 0.800s 12.674us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.410s 53.119us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.410s 53.119us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.880s 49.660us 1 1 100.00
keymgr_csr_rw 1.220s 113.153us 1 1 100.00
keymgr_csr_aliasing 2.810s 69.601us 1 1 100.00
keymgr_same_csr_outstanding 1.850s 165.685us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.880s 49.660us 1 1 100.00
keymgr_csr_rw 1.220s 113.153us 1 1 100.00
keymgr_csr_aliasing 2.810s 69.601us 1 1 100.00
keymgr_same_csr_outstanding 1.850s 165.685us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
keymgr_tl_intg_err 6.890s 988.599us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.030s 329.086us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.030s 329.086us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.030s 329.086us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.030s 329.086us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 3.840s 225.481us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 6.890s 988.599us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.030s 329.086us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 4.640s 122.678us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 10.960s 1.993ms 1 1 100.00
keymgr_csr_rw 1.220s 113.153us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 10.960s 1.993ms 1 1 100.00
keymgr_csr_rw 1.220s 113.153us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 10.960s 1.993ms 1 1 100.00
keymgr_csr_rw 1.220s 113.153us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.730s 78.078us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 7.450s 1.215ms 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 7.450s 1.215ms 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 10.960s 1.993ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.810s 43.819us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 3.150s 475.553us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.730s 78.078us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 3.150s 475.553us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 3.150s 475.553us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 3.150s 475.553us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 8.620s 1.001ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 3.150s 475.553us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 12.310s 1.147ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00