KMAC/MASKED Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	4.870s	135.393us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	17.358us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.060s	60.912us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.690s	161.255us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.900s	203.661us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.370s	190.922us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.060s	60.912us	1	1	100.00
		kmac_csr_aliasing	3.900s	203.661us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.870s	21.785us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.080s	31.548us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	35.559m	327.219ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.395m	24.255ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.280s	46.309us	0	1	0.00
		kmac_test_vectors_sha3_256	27.240s	3.810ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.059m	13.515ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.230s	1.181ms	1	1	100.00
		kmac_test_vectors_shake_128	2.487m	8.847ms	1	1	100.00
		kmac_test_vectors_shake_256	4.805m	10.771ms	1	1	100.00
		kmac_test_vectors_kmac	2.830s	531.812us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.890s	468.041us	1	1	100.00
V2	sideload	kmac_sideload	59.000s	2.156ms	1	1	100.00
V2	app	kmac_app	6.420s	449.342us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.062m	12.563ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.095m	10.226ms	1	1	100.00
V2	error	kmac_error	29.020s	1.647ms	1	1	100.00
V2	key_error	kmac_key_error	5.880s	2.874ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.040s	367.792us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.490s	1.067ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.340s	767.706us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	24.090s	6.079ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.600s	78.264us	1	1	100.00
V2	stress_all	kmac_stress_all	1.552m	3.733ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.940s	19.608us	1	1	100.00
V2	alert_test	kmac_alert_test	1.010s	16.006us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.640s	151.039us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.640s	151.039us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	17.358us	1	1	100.00
		kmac_csr_rw	1.060s	60.912us	1	1	100.00
		kmac_csr_aliasing	3.900s	203.661us	1	1	100.00
		kmac_same_csr_outstanding	1.920s	85.002us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	17.358us	1	1	100.00
		kmac_csr_rw	1.060s	60.912us	1	1	100.00
		kmac_csr_aliasing	3.900s	203.661us	1	1	100.00
		kmac_same_csr_outstanding	1.920s	85.002us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.360s	34.912us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.360s	34.912us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.360s	34.912us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.360s	34.912us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.330s	1.559ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	41.290s	4.404ms	1	1	100.00
		kmac_tl_intg_err	2.580s	240.733us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.580s	240.733us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.600s	78.264us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	4.870s	135.393us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	59.000s	2.156ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.360s	34.912us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	41.290s	4.404ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	41.290s	4.404ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	41.290s	4.404ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	4.870s	135.393us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.600s	78.264us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	41.290s	4.404ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.666m	48.852ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	4.870s	135.393us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.202m	8.968ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_224 has 1 failures.

    • 0.kmac_test_vectors_sha3_224.65264870737618912808244699681587099631337172858142093135937218518791071338793
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log

        UVM_ERROR @  46308769 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  46308769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.81382349395047650616731522049726634185263283890819324929821144348668631362804
      Line 383, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8967733889 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 8967733889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---