OTBN Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 10.000s 71.371us 0 1 0.00
V1 single_binary otbn_single 5.000s 115.810us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 23.237us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 18.595us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 263.141us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 27.310us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 5.000s 153.812us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 18.595us 1 1 100.00
otbn_csr_aliasing 3.000s 27.310us 1 1 100.00
V1 mem_walk otbn_mem_walk 16.000s 259.540us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 186.340us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 18.000s 262.557us 0 1 0.00
V2 multi_error otbn_multi_err 29.000s 657.135us 0 1 0.00
V2 back_to_back otbn_multi 46.000s 147.552us 0 1 0.00
V2 stress_all otbn_stress_all 4.367m 1.417ms 0 1 0.00
V2 lc_escalation otbn_escalate 10.000s 219.213us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 26.464us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 5.000s 131.318us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 18.379us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 18.138us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 189.512us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 189.512us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 23.237us 1 1 100.00
otbn_csr_rw 4.000s 18.595us 1 1 100.00
otbn_csr_aliasing 3.000s 27.310us 1 1 100.00
otbn_same_csr_outstanding 4.000s 73.478us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 23.237us 1 1 100.00
otbn_csr_rw 4.000s 18.595us 1 1 100.00
otbn_csr_aliasing 3.000s 27.310us 1 1 100.00
otbn_same_csr_outstanding 4.000s 73.478us 1 1 100.00
V2 TOTAL 4 11 36.36
V2S mem_integrity otbn_imem_err 7.000s 15.188us 0 1 0.00
otbn_dmem_err 9.000s 31.075us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 11.000s 395.346us 0 1 0.00
otbn_controller_ispr_rdata_err 6.000s 53.717us 0 1 0.00
otbn_mac_bignum_acc_err 8.000s 56.848us 0 1 0.00
otbn_urnd_err 7.000s 17.688us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 45.126us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 38.357us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 20.398us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 7.000s 56.295us 0 1 0.00
otbn_tl_intg_err 8.000s 234.978us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 11.000s 349.993us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S prim_count_check otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 10.000s 71.371us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 31.075us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 7.000s 15.188us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 8.000s 234.978us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 10.000s 219.213us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 7.000s 15.188us 0 1 0.00
otbn_dmem_err 9.000s 31.075us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 26.464us 0 1 0.00
otbn_illegal_mem_acc 4.000s 45.126us 1 1 100.00
otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 7.000s 15.188us 0 1 0.00
otbn_dmem_err 9.000s 31.075us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 26.464us 0 1 0.00
otbn_illegal_mem_acc 4.000s 45.126us 1 1 100.00
otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 10.000s 219.213us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 7.000s 15.188us 0 1 0.00
otbn_dmem_err 9.000s 31.075us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 26.464us 0 1 0.00
otbn_illegal_mem_acc 4.000s 45.126us 1 1 100.00
otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 13.128us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 15.037us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 17.000s 49.987us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 17.000s 49.987us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 4.000s 52.278us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 6.000s 55.873us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 32.406us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 32.406us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.000s 18.186us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 46.000s 147.552us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 10.000s 117.161us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 5.000s 115.810us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 7.000s 56.295us 0 1 0.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 1.117m 337.085us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 41 43.90

Failure Buckets