PATTGEN Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	31.274us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	16.373us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	13.339us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	481.737us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	17.868us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	14.073us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	13.339us	1	1	100.00
		pattgen_csr_aliasing	2.000s	17.868us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	2.567m	22.545ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	1.000s	52.069us	1	1	100.00
V2	error	pattgen_error	1.000s	45.915us	1	1	100.00
V2	stress_all	pattgen_stress_all	35.000s	5.767ms	1	1	100.00
V2	alert_test	pattgen_alert_test	2.000s	26.030us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	14.086us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	117.229us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	117.229us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	16.373us	1	1	100.00
		pattgen_csr_rw	1.000s	13.339us	1	1	100.00
		pattgen_csr_aliasing	2.000s	17.868us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	24.299us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	16.373us	1	1	100.00
		pattgen_csr_rw	1.000s	13.339us	1	1	100.00
		pattgen_csr_aliasing	2.000s	17.868us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	24.299us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	107.838us	1	1	100.00
		pattgen_sec_cm	2.000s	141.968us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	107.838us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	9.000s	3.802ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.167m	10.013ms	0	1	0.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.95145609201371044194386447030579069596629331638557772356314305577523263170614
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10012979394 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf3da3010, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
        UVM_INFO @ 10012979394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.91663103245843088435476041650685084450103824493159167431376119027637398156885
      Line 110, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 429605806 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 429613036 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 429613036 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 429693036 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]