ROM_CTRL/64KB Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.910s 313.278us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.740s 4.248ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.860s 550.825us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.170s 205.521us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.820s 2.392ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.680s 726.783us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.860s 550.825us 1 1 100.00
rom_ctrl_csr_aliasing 5.820s 2.392ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.900s 214.008us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.170s 906.837us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.030s 1.060ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 32.840s 1.184ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.220s 710.366us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 9.810s 420.639us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.880s 3.338ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.880s 3.338ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.740s 4.248ms 1 1 100.00
rom_ctrl_csr_rw 6.860s 550.825us 1 1 100.00
rom_ctrl_csr_aliasing 5.820s 2.392ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.260s 393.271us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.740s 4.248ms 1 1 100.00
rom_ctrl_csr_rw 6.860s 550.825us 1 1 100.00
rom_ctrl_csr_aliasing 5.820s 2.392ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.260s 393.271us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 34.580s 1.641ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 7.688m 3.704ms 1 1 100.00
rom_ctrl_tl_intg_err 1.679m 651.997us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 7.688m 3.704ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 7.688m 3.704ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 7.688m 3.704ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 7.688m 3.704ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.910s 313.278us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.910s 313.278us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.910s 313.278us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.679m 651.997us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.220s 710.366us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.215m 3.192ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 34.580s 1.641ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 7.688m 3.704ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.971m 4.812ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00