RV_TIMER Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.830s	188.966us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	21.704us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.690s	52.179us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.760s	190.423us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.810s	178.305us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.800s	54.193us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.690s	52.179us	1	1	100.00
		rv_timer_csr_aliasing	0.810s	178.305us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.680s	301.468us	0	1	0.00
V2	disabled	rv_timer_disabled	2.900s	2.062ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.840s	8.519ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.840s	8.519ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.210s	334.931us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.620s	52.822us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.620s	10.624us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.360s	36.310us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.360s	36.310us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	21.704us	1	1	100.00
		rv_timer_csr_rw	0.690s	52.179us	1	1	100.00
		rv_timer_csr_aliasing	0.810s	178.305us	1	1	100.00
		rv_timer_same_csr_outstanding	0.720s	19.013us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	21.704us	1	1	100.00
		rv_timer_csr_rw	0.690s	52.179us	1	1	100.00
		rv_timer_csr_aliasing	0.810s	178.305us	1	1	100.00
		rv_timer_same_csr_outstanding	0.720s	19.013us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.000s	113.852us	1	1	100.00
		rv_timer_tl_intg_err	1.140s	170.425us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.140s	170.425us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.780s	120.212us	0	1	0.00
V3	max_value	rv_timer_max	0.710s	85.373us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	42.320s	14.029ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.7671409168180341908975496049519163943162036608457854195720962899452482474098
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 120211667 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x45fa1104) == 0x1
        UVM_INFO @ 120211667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.41479403480830789639097977992525708865528671129466967238200468307594709084094
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 301468138 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb6d9eb04) == 0x1
        UVM_INFO @ 301468138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.95888531071652187801575808201296698983211364311880614287452450155463189412019
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  85373285 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  85373285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---