SPI_DEVICE/1R1W Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.529m	111.963ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.900s	16.805us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.890s	154.796us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.930s	541.920us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.310s	1.255ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.990s	703.736us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.890s	154.796us	1	1	100.00
		spi_device_csr_aliasing	11.310s	1.255ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.840s	36.456us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.720s	335.048us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.100s	155.225us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.880s	10.226us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	5.654us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.470s	317.900us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.470s	317.900us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.170s	6.277ms	1	1	100.00
		spi_device_tpm_sts_read	0.800s	101.960us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.040s	1.387ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.890s	114.121us	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.810s	1.418ms	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.810s	1.418ms	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.050s	729.123us	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.050s	729.123us	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.050s	729.123us	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.050s	729.123us	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.050s	729.123us	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.700s	6.550ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	26.490s	3.781ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	26.490s	3.781ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	26.490s	3.781ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	21.900s	6.217ms	1	1	100.00
		spi_device_read_buffer_direct	4.000s	822.072us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	26.490s	3.781ms	1	1	100.00
		spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.156m	37.983ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.900s	1.143ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.900s	1.143ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.529m	111.963ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	22.400s	2.826ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.040s	52.473us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.870s	49.426us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.850s	13.109us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.610s	210.985us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.610s	210.985us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.900s	16.805us	1	1	100.00
		spi_device_csr_rw	1.890s	154.796us	1	1	100.00
		spi_device_csr_aliasing	11.310s	1.255ms	1	1	100.00
		spi_device_same_csr_outstanding	2.560s	504.158us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.900s	16.805us	1	1	100.00
		spi_device_csr_rw	1.890s	154.796us	1	1	100.00
		spi_device_csr_aliasing	11.310s	1.255ms	1	1	100.00
		spi_device_same_csr_outstanding	2.560s	504.158us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.200s	53.362us	1	1	100.00
		spi_device_tl_intg_err	4.850s	105.940us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	4.850s	105.940us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	40.870s	3.273ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.78970521512480870032587237049874181659317787556961893554182859507517998310005
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   7610782 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[20])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   7610782 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   7610782 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[916])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.54668879688915895955906930606818888421999577195049285954491227507991355936336
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3285460 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17804d [101111000000001001101] vs 0x0 [0])
        UVM_ERROR @   3356460 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1b86da [110111000011011011010] vs 0x0 [0])
        UVM_ERROR @   3414460 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xafea78 [101011111110101001111000] vs 0x0 [0])
        UVM_ERROR @   3424460 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd1d255 [110100011101001001010101] vs 0x0 [0])
        UVM_ERROR @   3458460 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc5bf5d [110001011011111101011101] vs 0x0 [0])