SPI_DEVICE/2P Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 46.090s 32.204ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.120s 33.628us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.410s 365.608us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 26.120s 5.318ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 5.710s 115.657us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 1.570s 106.045us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.410s 365.608us 1 1 100.00
spi_device_csr_aliasing 5.710s 115.657us 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.860s 40.773us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.890s 62.650us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.000s 16.863us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.110s 25.901us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 0.830s 15.838us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 0.890s 120.938us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 0.890s 120.938us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 2.260s 2.454ms 1 1 100.00
spi_device_tpm_sts_read 0.730s 32.711us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 25.090s 27.249ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 6.430s 9.744ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 3.250s 4.903ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 3.250s 4.903ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 8.760s 1.142ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 8.760s 1.142ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 8.760s 1.142ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 8.760s 1.142ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 8.760s 1.142ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 5.240s 1.740ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 15.800s 6.217ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 15.800s 6.217ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 15.800s 6.217ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 2.830s 75.625us 1 1 100.00
spi_device_read_buffer_direct 4.990s 1.772ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 15.800s 6.217ms 1 1 100.00
spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.036m 46.036ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 9.680s 2.651ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 9.680s 2.651ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 46.090s 32.204ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 32.790s 7.108ms 1 1 100.00
V2 stress_all spi_device_stress_all 2.628m 22.551ms 1 1 100.00
V2 alert_test spi_device_alert_test 0.970s 29.764us 1 1 100.00
V2 intr_test spi_device_intr_test 0.820s 13.117us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 2.830s 157.091us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 2.830s 157.091us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.120s 33.628us 1 1 100.00
spi_device_csr_rw 1.410s 365.608us 1 1 100.00
spi_device_csr_aliasing 5.710s 115.657us 1 1 100.00
spi_device_same_csr_outstanding 1.620s 55.399us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.120s 33.628us 1 1 100.00
spi_device_csr_rw 1.410s 365.608us 1 1 100.00
spi_device_csr_aliasing 5.710s 115.657us 1 1 100.00
spi_device_same_csr_outstanding 1.620s 55.399us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.480s 488.174us 1 1 100.00
spi_device_tl_intg_err 15.460s 3.219ms 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 15.460s 3.219ms 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 1.202m 19.105ms 1 1 100.00
TOTAL 33 33 100.00