SPI_HOST Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	29.000s	1.053ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	19.907us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	52.159us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	539.749us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	57.044us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	258.283us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	52.159us	1	1	100.00
		spi_host_csr_aliasing	2.000s	57.044us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	57.667us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	150.340us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	61.356us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	1.275ms	1	1	100.00
		spi_host_error_cmd	2.000s	19.227us	1	1	100.00
		spi_host_event	13.000s	12.406ms	1	1	100.00
V2	clock_rate	spi_host_speed	1.000s	26.514us	1	1	100.00
V2	speed	spi_host_speed	1.000s	26.514us	1	1	100.00
V2	chip_select_timing	spi_host_speed	1.000s	26.514us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	11.000s	718.076us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	109.504us	1	1	100.00
V2	cpol_cpha	spi_host_speed	1.000s	26.514us	1	1	100.00
V2	full_cycle	spi_host_speed	1.000s	26.514us	1	1	100.00
V2	duplex	spi_host_smoke	29.000s	1.053ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	29.000s	1.053ms	1	1	100.00
V2	stress_all	spi_host_stress_all	39.000s	3.693ms	1	1	100.00
V2	spien	spi_host_spien	15.000s	2.131ms	1	1	100.00
V2	stall	spi_host_status_stall	3.000s	372.085us	0	1	0.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	79.530us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	1.275ms	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	14.434us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	27.383us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	116.182us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	116.182us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	19.907us	1	1	100.00
		spi_host_csr_rw	2.000s	52.159us	1	1	100.00
		spi_host_csr_aliasing	2.000s	57.044us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	22.679us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	19.907us	1	1	100.00
		spi_host_csr_rw	2.000s	52.159us	1	1	100.00
		spi_host_csr_aliasing	2.000s	57.044us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	22.679us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	88.842us	1	1	100.00
		spi_host_sec_cm	2.000s	151.671us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	88.842us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.767m	5.806ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
  • Test spi_host_status_stall has 1 failures.

    • 0.spi_host_status_stall.98278761299313852008282621302183664715471228438954933807448026496351068547890
      Line 1387, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log

        UVM_ERROR @ 372085438 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
        UVM_INFO @ 372085438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---