SRAM_CTRL/MAIN Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	24.750s	2.576ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.920s	48.611us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.950s	29.444us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.910s	467.298us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.020s	124.705us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.200s	481.973us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.950s	29.444us	1	1	100.00
		sram_ctrl_csr_aliasing	1.020s	124.705us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.550m	2.081ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	57.320s	5.137ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.207m	9.019ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.201m	18.404ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	7.754m	115.978ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.344m	59.822ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.410s	14.794ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.625m	267.774ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	42.330s	1.680ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.765m	68.008ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.131m	3.051ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	35.790s	3.055ms	1	1	100.00
		sram_ctrl_throughput_w_readback	32.640s	3.289ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.429m	22.752ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.830s	4.177ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.214h	216.650ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.820s	17.130us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.120s	63.004us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.120s	63.004us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.920s	48.611us	1	1	100.00
		sram_ctrl_csr_rw	0.950s	29.444us	1	1	100.00
		sram_ctrl_csr_aliasing	1.020s	124.705us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	40.107us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.920s	48.611us	1	1	100.00
		sram_ctrl_csr_rw	0.950s	29.444us	1	1	100.00
		sram_ctrl_csr_aliasing	1.020s	124.705us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	40.107us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.140s	3.748ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.850s	4.508us	0	1	0.00
		sram_ctrl_tl_intg_err	1.520s	764.128us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.850s	4.508us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.520s	764.128us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.429m	22.752ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.429m	22.752ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.950s	29.444us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.625m	267.774ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.625m	267.774ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.625m	267.774ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.410s	14.794ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.980s	1.281ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.140s	3.748ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.950s	3.038ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	24.750s	2.576ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	24.750s	2.576ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.625m	267.774ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.850s	4.508us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.410s	14.794ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.850s	4.508us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.850s	4.508us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	24.750s	2.576ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.850s	4.508us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	24.640s	6.218ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.7357697381316483627863474172572756989838939859637582814085369653080855320649
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4507509 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4507509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---