SRAM_CTRL/RET Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.970s	1.457ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.770s	52.439us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	20.843us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.090s	98.625us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	72.717us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.000s	62.993us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	20.843us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	72.717us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.540s	179.624us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.540s	91.502us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.391m	12.025ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.595m	14.413ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.060s	4.598ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.577m	15.106ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.890s	1.527ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.917m	30.881ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	8.670s	1.030ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.579m	62.798ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	11.960s	374.782us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	36.470s	149.361us	1	1	100.00
		sram_ctrl_throughput_w_readback	39.730s	595.901us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.273m	28.801ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.920s	53.396us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	8.870m	15.669ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.930s	14.043us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.130s	74.198us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.130s	74.198us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.770s	52.439us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	20.843us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	72.717us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	12.910us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.770s	52.439us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	20.843us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	72.717us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	12.910us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.440s	1.533ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.000s	31.507us	0	1	0.00
		sram_ctrl_tl_intg_err	1.970s	286.140us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.000s	31.507us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.970s	286.140us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.273m	28.801ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.273m	28.801ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	20.843us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.917m	30.881ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.917m	30.881ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.917m	30.881ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.890s	1.527ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.980s	112.059us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.440s	1.533ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.220s	324.608us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.970s	1.457ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.970s	1.457ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.917m	30.881ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.000s	31.507us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.890s	1.527ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.000s	31.507us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.000s	31.507us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.970s	1.457ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.000s	31.507us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.810m	1.503ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.100039006028500480344410400679292029874051916906712243493073133249697222902408
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  31507041 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  31507041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---