SYSRST_CTRL Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.680s 2.109ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.040s 2.501ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.010s 2.436ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.780s 2.327ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.390s 4.043ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.620s 2.038ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 18.940s 38.154ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 6.510s 2.598ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.380s 2.508ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.620s 2.038ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.510s 2.598ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 3.554m 104.238ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 32.880s 76.392ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.190s 3.258ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 4.770s 3.581ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 1.090s 2.570ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.670s 2.111ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 7.830s 3.573ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 5.410s 2.614ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 35.680s 760.308ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.181m 37.096ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 7.915m 246.952ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.640s 2.029ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 4.190s 2.012ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.070s 2.690ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.070s 2.690ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.390s 4.043ms 1 1 100.00
sysrst_ctrl_csr_rw 4.620s 2.038ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.510s 2.598ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.070s 7.501ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.390s 4.043ms 1 1 100.00
sysrst_ctrl_csr_rw 4.620s 2.038ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.510s 2.598ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.070s 7.501ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 11.010s 22.067ms 1 1 100.00
sysrst_ctrl_tl_intg_err 8.310s 22.602ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 8.310s 22.602ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 3.980s 8.991ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00