UART Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: aae3d67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.250s	559.494us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.820s	13.640us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.780s	15.237us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.040s	61.740us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.940s	18.660us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.940s	40.092us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.780s	15.237us	1	1	100.00
		uart_csr_aliasing	0.940s	18.660us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	37.560s	166.440ms	1	1	100.00
V2	parity	uart_smoke	1.250s	559.494us	1	1	100.00
		uart_tx_rx	37.560s	166.440ms	1	1	100.00
V2	parity_error	uart_intr	15.370s	22.039ms	1	1	100.00
		uart_rx_parity_err	35.780s	54.995ms	1	1	100.00
V2	watermark	uart_tx_rx	37.560s	166.440ms	1	1	100.00
		uart_intr	15.370s	22.039ms	1	1	100.00
V2	fifo_full	uart_fifo_full	30.820s	26.897ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	3.460s	2.803ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.490s	24.480ms	1	1	100.00
V2	rx_frame_err	uart_intr	15.370s	22.039ms	1	1	100.00
V2	rx_break_err	uart_intr	15.370s	22.039ms	1	1	100.00
V2	rx_timeout	uart_intr	15.370s	22.039ms	1	1	100.00
V2	perf	uart_perf	10.906m	17.095ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.970s	8.553ms	1	1	100.00
V2	line_loopback	uart_loopback	5.970s	8.553ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.380s	2.189ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.400s	3.099ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.810s	1.965ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.110s	1.482ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.002m	134.920ms	1	1	100.00
V2	stress_all	uart_stress_all	4.596m	80.168ms	0	1	0.00
V2	alert_test	uart_alert_test	0.840s	12.155us	1	1	100.00
V2	intr_test	uart_intr_test	0.730s	14.012us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.600s	276.514us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.600s	276.514us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.820s	13.640us	1	1	100.00
		uart_csr_rw	0.780s	15.237us	1	1	100.00
		uart_csr_aliasing	0.940s	18.660us	1	1	100.00
		uart_same_csr_outstanding	0.720s	99.463us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.820s	13.640us	1	1	100.00
		uart_csr_rw	0.780s	15.237us	1	1	100.00
		uart_csr_aliasing	0.940s	18.660us	1	1	100.00
		uart_same_csr_outstanding	0.720s	99.463us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.950s	149.372us	1	1	100.00
		uart_tl_intg_err	1.190s	185.012us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.190s	185.012us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	54.050s	4.605ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.75859804333423157177594573793440348397941170791098218494853595242769035437652
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  24278805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 374918805 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 374918805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 430838805 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 430838805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.18892981353132664465313766079645906013891010642987705878024209529332017750905
      Line 164, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 80139325260 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 80139488524 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 80140457904 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 80150478232 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 80150478232 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0