CHIP Simulation Results

Thursday October 16 2025 17:16:32 UTC

GitHub Revision: `aae3d67`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.823m	2.834ms	1	1	100.00
		chip_sw_example_rom	1.094m	2.236ms	1	1	100.00
		chip_sw_example_manufacturer	2.497m	2.577ms	1	1	100.00
		chip_sw_example_concurrency	2.601m	3.070ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.892m	6.851ms	1	1	100.00
V1	csr_rw	chip_csr_rw	7.761m	6.500ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.949m	3.660ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.056h	26.909ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	5.019m	6.107ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.056h	26.909ms	1	1	100.00
		chip_csr_rw	7.761m	6.500ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.580s	165.481us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.029m	4.035ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.029m	4.035ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.029m	4.035ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.587m	4.043ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.587m	4.043ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.353m	3.690ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.282m	4.260ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.432m	4.408ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	6.897m	4.830ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.518m	4.070ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.434m	8.489ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.768m	4.999ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.768m	4.999ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.325m	2.749ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.062m	3.337ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.265m	3.694ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.391m	3.997ms	1	1	100.00
		chip_tap_straps_testunlock0	1.841m	3.616ms	1	1	100.00
		chip_tap_straps_rma	3.539m	4.405ms	1	1	100.00
		chip_tap_straps_prod	12.111m	11.058ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.367m	3.196ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.946m	9.052ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.341m	4.874ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.341m	4.874ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.550m	8.058ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	37.871m	23.662ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.517m	4.125ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.015m	6.146ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.322m	19.317ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.140m	2.707ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	14.961m	7.889ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.359m	3.077ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.243m	9.397ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.974m	3.198ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.309m	4.143ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.917m	2.170ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.969m	3.045ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	4.766m	5.513ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.837m	4.829ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.749m	2.512ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.837m	4.829ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.979m	2.795ms	1	1	100.00
		chip_sw_aes_smoketest	2.687m	2.850ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.245m	3.197ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.997m	2.961ms	1	1	100.00
		chip_sw_csrng_smoketest	2.259m	2.584ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.258m	5.927ms	1	1	100.00
		chip_sw_gpio_smoketest	3.285m	2.875ms	1	1	100.00
		chip_sw_hmac_smoketest	3.672m	3.340ms	1	1	100.00
		chip_sw_kmac_smoketest	2.455m	2.803ms	1	1	100.00
		chip_sw_otbn_smoketest	11.872m	6.691ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.326m	4.685ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.182m	6.238ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.958m	2.540ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.012m	2.987ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.059m	2.627ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.820m	2.737ms	1	1	100.00
		chip_sw_uart_smoketest	1.976m	2.603ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.446m	2.318ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.875m	4.226ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.084h	60.090ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	43.163m	15.797ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.035m	14.923ms	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.913m	3.010ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.728m	3.415ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.917h	55.718ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.980h	56.625ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	42.060s	2.122ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	42.060s	2.122ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.056h	26.909ms	1	1	100.00
		chip_same_csr_outstanding	40.512m	30.419ms	1	1	100.00
		chip_csr_hw_reset	3.892m	6.851ms	1	1	100.00
		chip_csr_rw	7.761m	6.500ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.056h	26.909ms	1	1	100.00
		chip_same_csr_outstanding	40.512m	30.419ms	1	1	100.00
		chip_csr_hw_reset	3.892m	6.851ms	1	1	100.00
		chip_csr_rw	7.761m	6.500ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	35.610s	573.317us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.310s	53.859us	1	1	100.00
		xbar_smoke_large_delays	1.048m	9.837ms	1	1	100.00
		xbar_smoke_slow_rsp	36.030s	3.706ms	1	1	100.00
		xbar_random_zero_delays	32.620s	556.396us	1	1	100.00
		xbar_random_large_delays	3.721m	36.402ms	1	1	100.00
		xbar_random_slow_rsp	4.323m	30.970ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	7.270s	36.305us	1	1	100.00
		xbar_error_and_unmapped_addr	17.350s	250.062us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	35.970s	1.917ms	1	1	100.00
		xbar_error_and_unmapped_addr	17.350s	250.062us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	49.260s	1.061ms	1	1	100.00
		xbar_access_same_device_slow_rsp	2.620m	16.950ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	41.040s	2.287ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.984m	8.378ms	1	1	100.00
		xbar_stress_all_with_error	2.974m	3.831ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.547m	2.838ms	1	1	100.00
		xbar_stress_all_with_reset_error	7.560s	29.109us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	43.163m	15.797ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	39.666m	28.329ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.727m	15.528ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.816m	11.421ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.321m	15.576ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.247m	15.348ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	45.485m	18.323ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.663m	14.928ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.970s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.860s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.710s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.740s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.580s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.220s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.940s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	24.170s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.500s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.340s	10.280us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.680s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	19.320s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.110s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.440s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.920s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.830s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.070s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.420s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.430s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.360s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.470s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	23.120s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.090s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.420s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.510s	10.180us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.845m	12.091ms	1	1	100.00
		rom_e2e_asm_init_dev	41.999m	15.537ms	1	1	100.00
		rom_e2e_asm_init_prod	41.426m	15.210ms	1	1	100.00
		rom_e2e_asm_init_prod_end	43.186m	18.303ms	1	1	100.00
		rom_e2e_asm_init_rma	40.937m	14.298ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	40.750m	14.749ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.757m	15.792ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.486m	14.789ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.178m	16.036ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.114m	34.644ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.114m	34.644ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.291m	3.338ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.140m	2.707ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.579m	2.838ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.780m	3.175ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	26.492m	12.901ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.123m	2.491ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.098m	6.322ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.267m	5.672ms	1	1	100.00
		chip_plic_all_irqs_10	4.413m	3.568ms	1	1	100.00
		chip_plic_all_irqs_20	5.862m	4.626ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.812m	3.150ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.456m	9.398ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.793m	4.296ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.444m	2.651ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.224m	7.717ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.840m	6.311ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.915m	7.975ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.402h	255.246ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.557m	4.138ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.326m	4.685ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.557m	4.138ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.721m	10.251ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.721m	10.251ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.172m	7.378ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.302m	5.578ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.689m	5.412ms	1	1	100.00
		chip_sw_aes_idle	2.780m	3.175ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.486m	3.374ms	1	1	100.00
		chip_sw_kmac_idle	2.088m	3.046ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.421m	4.812ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.886m	4.597ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.827m	4.707ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.378m	5.257ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.116m	11.166ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.877m	4.280ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.473m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.437m	4.865ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.867m	4.637ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.101m	4.146ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.447m	4.681ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.550m	8.058ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.876m	5.500ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.437m	4.865ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.867m	4.637ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.517m	4.125ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.015m	6.146ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.322m	19.317ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.140m	2.707ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	14.961m	7.889ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.359m	3.077ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.243m	9.397ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.974m	3.198ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.309m	4.143ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.917m	2.170ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.121m	2.953ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.292m	4.397ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.439m	7.242ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.660m	24.445ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.470m	3.127ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.048m	3.210ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.683m	10.657ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.741m	3.289ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.341m	4.682ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.926m	20.773ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	47.365m	26.645ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.550m	8.058ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.689m	4.689ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.490m	3.877ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.224m	7.717ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.254m	6.305ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.317m	3.561ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.710m	6.364ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.976m	2.153ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.205h	25.266ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.062m	2.421ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.028m	5.919ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.062m	2.421ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.254m	6.305ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.745m	3.377ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	25.313m	26.801ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.226m	5.950ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.015m	6.146ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.815m	4.031ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.517m	4.125ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.139m	44.610ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	25.313m	26.801ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.973m	3.649ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.894m	7.717ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.360m	5.341ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.139m	44.610ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.360m	5.341ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.360m	5.341ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.360m	5.341ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.360m	5.341ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.897m	8.750ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.118m	4.991ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.129m	4.828ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.129m	4.828ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.828m	2.562ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.359m	3.077ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.486m	3.374ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.201m	3.687ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.665m	3.547ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.792m	4.766ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.441m	4.450ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.491m	4.912ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.104m	3.865ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.894m	7.717ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.243m	9.397ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.802m	9.941ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	26.492m	12.901ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	41.623m	14.059ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.618m	3.374ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.257m	2.745ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.974m	3.198ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.894m	7.717ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.766m	2.750ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	19.729m	9.061ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.088m	3.046ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.098m	6.322ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.391m	3.997ms	1	1	100.00
		chip_tap_straps_rma	3.539m	4.405ms	1	1	100.00
		chip_tap_straps_prod	12.111m	11.058ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.632m	2.646ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	28.839m	12.248ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.360m	5.341ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.139m	44.610ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.413m	2.921ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.938m	5.898ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.258m	5.310ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.923m	7.530ms	0	1	0.00
		chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.894m	7.717ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.347m	8.871ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.151m	7.811ms	1	1	100.00
		chip_prim_tl_access	3.897m	8.750ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.876m	5.500ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.877m	4.280ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.473m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.437m	4.865ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.867m	4.637ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.101m	4.146ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.447m	4.681ms	1	1	100.00
		chip_tap_straps_dev	3.391m	3.997ms	1	1	100.00
		chip_tap_straps_rma	3.539m	4.405ms	1	1	100.00
		chip_tap_straps_prod	12.111m	11.058ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.917m	11.382ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.169m	3.991ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.617m	3.238ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.685m	3.454ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.332m	2.582ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.443m	31.984ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.917m	11.382ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.010h	50.680ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.074h	45.679ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.187m	8.449ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.366m	45.112ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.443m	31.984ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	53.810s	1.773ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.050m	2.052ms	1	1	100.00
		rom_volatile_raw_unlock	56.380s	2.165ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.246m	17.053ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.322m	19.317ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.689m	5.412ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.689m	5.412ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.689m	5.412ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.482m	3.222ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	25.313m	26.801ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.482m	3.222ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.894m	7.717ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.734m	4.445ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.788m	3.323ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	25.313m	26.801ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.482m	3.222ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.894m	7.717ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.734m	4.445ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.788m	3.323ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.507m	4.953ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.632m	2.646ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.413m	2.921ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.938m	5.898ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.258m	5.310ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.923m	7.530ms	0	1	0.00
		chip_sw_lc_ctrl_transition	10.498m	9.999ms	1	1	100.00
		chip_prim_tl_access	3.897m	8.750ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.897m	8.750ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.962m	8.174ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.418m	8.505ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.197m	27.943ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.110m	7.429ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.293m	7.192ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.188m	7.019ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.363m	21.075ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.689m	16.754ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.721m	10.251ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.696m	13.495ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.119m	4.114ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.418m	8.505ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.536m	3.058ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	35.854m	43.125ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.799m	6.974ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	6.136m	6.682ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.674m	21.382ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.134m	8.242ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	16.867m	11.470ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	17.627m	25.509ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.947m	3.572ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.347m	8.871ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.347m	8.871ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.867m	11.470ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.674m	21.382ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.119m	4.114ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.326m	4.685ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.427m	3.969ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.290m	4.942ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.042m	3.704ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.456m	9.398ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.747m	2.949ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.840m	6.311ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.599m	5.574ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.493m	4.792ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.930m	3.084ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.788m	3.323ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.290m	4.942ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.290m	4.942ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	14.920m	14.038ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.932m	13.864ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.427m	3.969ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.359m	4.994ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.982m	5.522ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.539m	4.405ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.917m	11.382ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.267m	5.672ms	1	1	100.00
		chip_plic_all_irqs_10	4.413m	3.568ms	1	1	100.00
		chip_plic_all_irqs_20	5.862m	4.626ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.837m	2.793ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.664m	3.145ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	43.163m	15.797ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.609m	6.712ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.806m	3.036ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.806m	3.473ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.782m	3.363ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.734m	4.445ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.309m	4.143ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.576m	6.539ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.624m	8.217ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.151m	7.811ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.341m	4.874ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.134m	8.242ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.395m	24.426ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.337m	2.221ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.752m	4.048ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.138m	4.262ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.395m	24.426ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.395m	24.426ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.859m	11.577ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.859m	11.577ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.108m	6.453ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.114m	34.644ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.342m	2.852ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.912m	2.758ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.077m	4.085ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.979m	3.358ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.499m	7.949ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.392h	31.790ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.042m	12.195ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.979m	2.320ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.146m	3.227ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.668m	2.902ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.584h	71.638ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.678m	4.447ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.475m	12.157ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.735m	10.258ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.744m	12.030ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.290m	4.036ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.219m	4.897ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.613m	4.586ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.447s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.658m	5.244ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.814m	2.736ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.863m	5.911ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.356m	7.578ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.609m	1.986ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.600m	5.209ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.118m	3.019ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.290m	4.538ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.064m	6.495ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.920m	4.302ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.867m	11.470ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.475m	12.157ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.735m	10.258ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.744m	12.030ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.170m	4.527ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.094m	5.302ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.550h	39.060ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.550h	39.060ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.779m	3.395ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.587m	4.043ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.582m	18.147ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.680m	3.354ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.282m	5.418ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	33.187m	31.084ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.485m	2.839ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.342m	2.960ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.344m	3.923ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.058s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.590m	3.244ms	1	1	100.00
		TOTAL			284	326	87.12

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.43055493943224040841931182276361704783189576604221550311127568798791090341454
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.62173539404741976044795420151812225661024824301028204088821856633174068859784
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.41326387599478081886573437672201244789372100212157027703853848800657118067626
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.47296378091200413857236133848710017191323332904711430241076710320354290626310
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.79080383245082287868747605180283181936015048797389917885500015436103869639065
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.56432293106046849894054987828418499876799771004957676833963185899006107618547
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.22498926912710190387948711196277078778048375801167132975955775664099128948244
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.59302012391571958166544819627522012357394312747118963228671138279594728335534
    Line 471, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.10058806288563717117189731772338116523006200686931759155980519272789848858491
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.15904508679366424276394759097352038604014400292324573363370048611383945306473
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.8015543864294805612071316602511668116678591714237639770228040651547380182406
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.27895441373507213623273704786902666128370334406313578442475977021779508077860
    Line 542, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.25300297894898384224072619922010330551168150632580500743032970422729453414176
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.13346454116637595483167927995009440140985987824835868738745682327198427682187
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.113365675049148416155409808964094488236257140609611413933043458782559681157414
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.152s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1324816357265979389077737166184266497315115473964576769923409673630602195756
    Line 512, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.72912136090753653079814559756791271448011320769351431517248390245904168249652
    Line 479, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.108482169298494213226621258828360467685505222257218063138441545978785792725083
    Line 531, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.111538005209181754207533567283623081666046519886787329661501359319776286584812
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.85685687787117905414057671330795925893218844502717526701793325111523683195168
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3035.989244 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3035.989244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.1065810528904552371851301715035013499507212035695081823246202847583797749482
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7529.628412 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7529.628412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.72460497701847521258070384889345088807719844637547664620873098815893418818146
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 31083.590844 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 31083.590844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@121922) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.53688813994632594313788913702435262697227454589965143886163245352904970685257
Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4942.062659 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@121922) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4942.062659 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.3776976499965010631965342446488977400112710834005119256013251083574219397466
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11576.835999 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11576.835999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.38244613347319828254420410678344865447736339030009850250656577336518654751721
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34643.504725 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34643.504725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1875136752595501151585910392490461759652516632711355495307873417866675623242
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2490.763915 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2490.763915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675491693803894822219098387755041471870480740417417685241202971445079588966
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2651.326994 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2651.326994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.5110885713186851079661934106917510770781607118780903763063445849770600158578
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.34106130292066785299067345068680186940412157087739362743818304913406519794172
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3687.469364 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3687.469364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35510) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.103495540097299606990396389263835266585103528118025730861138885388066548995655
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2122.236559 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35510) { a_addr: 'h107e0  a_data: 'h551bc1ac  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h19928  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2122.236559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.62822698403326153376380222650747959549733609474136839199799750805463456783565
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3010.208000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3010.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.9651744082342306690451878235348412402800385343489208927638791973822653970024
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3414.985000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3414.985000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.32717243822845904211629032108945770555941858162123630762897245281854194090889
    Line 457, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4447.131197 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4447.131197 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.98887951589951390060090753197099330119319260108897758825166361477833736888959
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.66510541691122470019399452987149909538201378191099867825817718034598504102642
    Line 540, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.7664487936670733458347214111697175634097932161032213511966469839342040648529
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 14922.518580 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 14922.518580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```