ADC_CTRL Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.250s	5.920ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.120s	1.217ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.890s	418.643us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	45.070s	26.549ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.420s	646.197us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.420s	442.404us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.890s	418.643us	1	1	100.00
		adc_ctrl_csr_aliasing	2.420s	646.197us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	7.358m	492.241ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	6.647m	495.654ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.538m	164.824ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.775m	489.168ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.530m	344.326ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	11.145m	404.235ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	7.656m	529.723ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.103m	157.486ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.110s	2.877ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	20.740s	45.734ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.129m	120.981ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	3.776m	489.646ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.100s	383.732us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.990s	525.549us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.130s	381.130us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.130s	381.130us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.120s	1.217ms	1	1	100.00
		adc_ctrl_csr_rw	0.890s	418.643us	1	1	100.00
		adc_ctrl_csr_aliasing	2.420s	646.197us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.010s	4.173ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.120s	1.217ms	1	1	100.00
		adc_ctrl_csr_rw	0.890s	418.643us	1	1	100.00
		adc_ctrl_csr_aliasing	2.420s	646.197us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.010s	4.173ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.950s	8.176ms	1	1	100.00
		adc_ctrl_tl_intg_err	14.960s	8.505ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	14.960s	8.505ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.660s	5.295ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00