CSRNG Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	2.000s	69.651us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	62.079us	1	1	100.00
V1	csr_rw	csrng_csr_rw	2.000s	20.758us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	7.000s	224.830us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	179.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.000s	43.472us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	2.000s	20.758us	1	1	100.00
		csrng_csr_aliasing	4.000s	179.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	5.000s	230.134us	1	1	100.00
V2	alerts	csrng_alert	10.000s	585.312us	1	1	100.00
V2	err	csrng_err	3.000s	24.017us	1	1	100.00
V2	cmds	csrng_cmds	53.000s	2.136ms	1	1	100.00
V2	life cycle	csrng_cmds	53.000s	2.136ms	1	1	100.00
V2	stress_all	csrng_stress_all	2.000s	13.629us	0	1	0.00
V2	intr_test	csrng_intr_test	1.000s	14.596us	1	1	100.00
V2	alert_test	csrng_alert_test	3.000s	26.267us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	7.000s	148.099us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	7.000s	148.099us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	62.079us	1	1	100.00
		csrng_csr_rw	2.000s	20.758us	1	1	100.00
		csrng_csr_aliasing	4.000s	179.000us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	150.165us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	62.079us	1	1	100.00
		csrng_csr_rw	2.000s	20.758us	1	1	100.00
		csrng_csr_aliasing	4.000s	179.000us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	150.165us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	3.000s	142.362us	1	1	100.00
		csrng_tl_intg_err	9.000s	992.327us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	2.000s	39.849us	1	1	100.00
		csrng_csr_rw	2.000s	20.758us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	10.000s	585.312us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	2.000s	13.629us	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	10.000s	585.312us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	2.000s	13.629us	0	1	0.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	10.000s	585.312us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	992.327us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
		csrng_sec_cm	3.000s	142.362us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	5.000s	230.134us	1	1	100.00
		csrng_err	3.000s	24.017us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.533m	11.312ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
  • Test csrng_stress_all has 1 failures.

    • 0.csrng_stress_all.92942982750863751251029108248207130293302987275927796735395637170629963357678
      Line 144, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log

        UVM_ERROR @  13629233 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  13629233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---