EDN Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.960s 18.699us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.820s 186.261us 1 1 100.00
V1 csr_rw edn_csr_rw 0.900s 15.349us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.210s 428.030us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.090s 38.928us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.950s 21.511us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.900s 15.349us 1 1 100.00
edn_csr_aliasing 1.090s 38.928us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 0.990s 50.000us 1 1 100.00
V2 csrng_commands edn_genbits 0.990s 50.000us 1 1 100.00
V2 genbits edn_genbits 0.990s 50.000us 1 1 100.00
V2 interrupts edn_intr 0.930s 24.124us 1 1 100.00
V2 alerts edn_alert 1.060s 86.528us 1 1 100.00
V2 errs edn_err 0.800s 43.567us 1 1 100.00
V2 disable edn_disable 0.840s 14.687us 1 1 100.00
edn_disable_auto_req_mode 1.030s 48.984us 1 1 100.00
V2 stress_all edn_stress_all 3.500s 1.110ms 1 1 100.00
V2 intr_test edn_intr_test 0.900s 14.035us 1 1 100.00
V2 alert_test edn_alert_test 0.890s 14.706us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.260s 271.648us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.260s 271.648us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.820s 186.261us 1 1 100.00
edn_csr_rw 0.900s 15.349us 1 1 100.00
edn_csr_aliasing 1.090s 38.928us 1 1 100.00
edn_same_csr_outstanding 1.040s 15.670us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.820s 186.261us 1 1 100.00
edn_csr_rw 0.900s 15.349us 1 1 100.00
edn_csr_aliasing 1.090s 38.928us 1 1 100.00
edn_same_csr_outstanding 1.040s 15.670us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.040s 501.978us 1 1 100.00
edn_tl_intg_err 1.460s 48.608us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.980s 19.537us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.060s 86.528us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.040s 501.978us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.040s 501.978us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.040s 501.978us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.040s 501.978us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.060s 86.528us 1 1 100.00
edn_sec_cm 6.040s 501.978us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.060s 86.528us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.460s 48.608us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets