HMAC Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.310s 126.643us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.860s 20.207us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.930s 24.710us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.240s 216.643us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.090s 412.015us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 12.777m 467.117ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.930s 24.710us 1 1 100.00
hmac_csr_aliasing 4.090s 412.015us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 26.610s 1.233ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.230m 3.832ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.620s 615.198us 1 1 100.00
hmac_test_sha384_vectors 6.405m 22.698ms 1 1 100.00
hmac_test_sha512_vectors 6.075m 10.560ms 1 1 100.00
hmac_test_hmac256_vectors 7.180s 760.465us 1 1 100.00
hmac_test_hmac384_vectors 8.760s 259.926us 1 1 100.00
hmac_test_hmac512_vectors 8.900s 1.166ms 1 1 100.00
V2 burst_wr hmac_burst_wr 2.160s 194.241us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 11.603m 5.829ms 1 1 100.00
V2 error hmac_error 1.054m 6.212ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 56.760s 9.816ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.310s 126.643us 1 1 100.00
hmac_long_msg 26.610s 1.233ms 1 1 100.00
hmac_back_pressure 1.230m 3.832ms 1 1 100.00
hmac_datapath_stress 11.603m 5.829ms 1 1 100.00
hmac_burst_wr 2.160s 194.241us 1 1 100.00
hmac_stress_all 50.600s 4.127ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.310s 126.643us 1 1 100.00
hmac_long_msg 26.610s 1.233ms 1 1 100.00
hmac_back_pressure 1.230m 3.832ms 1 1 100.00
hmac_datapath_stress 11.603m 5.829ms 1 1 100.00
hmac_wipe_secret 56.760s 9.816ms 1 1 100.00
hmac_test_sha256_vectors 8.620s 615.198us 1 1 100.00
hmac_test_sha384_vectors 6.405m 22.698ms 1 1 100.00
hmac_test_sha512_vectors 6.075m 10.560ms 1 1 100.00
hmac_test_hmac256_vectors 7.180s 760.465us 1 1 100.00
hmac_test_hmac384_vectors 8.760s 259.926us 1 1 100.00
hmac_test_hmac512_vectors 8.900s 1.166ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.310s 126.643us 1 1 100.00
hmac_long_msg 26.610s 1.233ms 1 1 100.00
hmac_back_pressure 1.230m 3.832ms 1 1 100.00
hmac_datapath_stress 11.603m 5.829ms 1 1 100.00
hmac_burst_wr 2.160s 194.241us 1 1 100.00
hmac_error 1.054m 6.212ms 1 1 100.00
hmac_wipe_secret 56.760s 9.816ms 1 1 100.00
hmac_test_sha256_vectors 8.620s 615.198us 1 1 100.00
hmac_test_sha384_vectors 6.405m 22.698ms 1 1 100.00
hmac_test_sha512_vectors 6.075m 10.560ms 1 1 100.00
hmac_test_hmac256_vectors 7.180s 760.465us 1 1 100.00
hmac_test_hmac384_vectors 8.760s 259.926us 1 1 100.00
hmac_test_hmac512_vectors 8.900s 1.166ms 1 1 100.00
hmac_stress_all 50.600s 4.127ms 1 1 100.00
V2 stress_all hmac_stress_all 50.600s 4.127ms 1 1 100.00
V2 alert_test hmac_alert_test 0.710s 20.782us 1 1 100.00
V2 intr_test hmac_intr_test 0.690s 15.252us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.820s 382.613us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.820s 382.613us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.860s 20.207us 1 1 100.00
hmac_csr_rw 0.930s 24.710us 1 1 100.00
hmac_csr_aliasing 4.090s 412.015us 1 1 100.00
hmac_same_csr_outstanding 1.390s 71.819us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.860s 20.207us 1 1 100.00
hmac_csr_rw 0.930s 24.710us 1 1 100.00
hmac_csr_aliasing 4.090s 412.015us 1 1 100.00
hmac_same_csr_outstanding 1.390s 71.819us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.970s 348.262us 1 1 100.00
hmac_tl_intg_err 3.430s 501.207us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.430s 501.207us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.310s 126.643us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.830s 113.152us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 14.606m 120.574ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.960s 97.486us 1 1 100.00
TOTAL 28 28 100.00