I2C Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	24.870s	2.114ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.830s	4.897ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.820s	70.150us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.730s	22.990us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.230s	354.368us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.170s	87.964us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.850s	71.273us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.730s	22.990us	1	1	100.00
		i2c_csr_aliasing	1.170s	87.964us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.140s	27.826us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	8.347m	23.828ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	8.280s	3.160ms	1	1	100.00
V2	host_override	i2c_host_override	0.790s	43.377us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	59.360s	6.859ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	41.230s	2.127ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.070s	93.915us	1	1	100.00
		i2c_host_fifo_fmt_empty	18.590s	1.038ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.430s	176.732us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.080m	3.612ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.950s	748.830us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.780s	144.795us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.270s	1.036ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	34.790s	37.952ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.670s	4.679ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	43.010s	10.978ms	1	1	100.00
		i2c_target_intr_smoke	5.780s	4.198ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.170s	594.645us	1	1	100.00
		i2c_target_fifo_reset_tx	1.000s	457.124us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.115m	31.038ms	1	1	100.00
		i2c_target_stress_rd	43.010s	10.978ms	1	1	100.00
		i2c_target_intr_stress_wr	21.490s	7.996ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.920s	5.615ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.090s	2.307ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.490s	1.310ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.020s	1.387ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.900s	457.246us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.350s	530.332us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	8.280s	3.160ms	1	1	100.00
		i2c_host_perf_precise	1.220s	97.989us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.950s	748.830us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.960s	107.175us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.960s	1.755ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.330s	583.870us	1	1	100.00
		i2c_target_nack_txstretch	1.430s	144.212us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.270s	2.608ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.840s	565.320us	1	1	100.00
V2	alert_test	i2c_alert_test	0.620s	15.405us	1	1	100.00
V2	intr_test	i2c_intr_test	0.820s	89.173us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.050s	197.106us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.050s	197.106us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.820s	70.150us	1	1	100.00
		i2c_csr_rw	0.730s	22.990us	1	1	100.00
		i2c_csr_aliasing	1.170s	87.964us	1	1	100.00
		i2c_same_csr_outstanding	0.940s	63.439us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.820s	70.150us	1	1	100.00
		i2c_csr_rw	0.730s	22.990us	1	1	100.00
		i2c_csr_aliasing	1.170s	87.964us	1	1	100.00
		i2c_same_csr_outstanding	0.940s	63.439us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.040s	512.326us	1	1	100.00
		i2c_sec_cm	0.940s	128.026us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.040s	512.326us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	25.380s	2.606ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.280s	462.069us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.380s	2.527ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.11479533782264851108912997909074109012544171463902105288119010438956967587212
      Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2606076041 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2606076041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.115643391449933621364818182652466995055863326944977881880142345778922931921095
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2527457139 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2527457139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.72683310804806932835286027595512988903008254884612495994616765423302538520010
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  27825951 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  27825951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.41770439147430750126448091452302450293778488910492930183985390525043541698402
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1036374409 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1036374409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.109987045051405330555927054527175832638872245666325798791400404893464516004042
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 462068604 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 462068604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---