KEYMGR Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.410s	112.845us	1	1	100.00
V1	random	keymgr_random	3.890s	148.152us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.990s	85.527us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.950s	42.380us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	21.170s	1.300ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.850s	641.898us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.250s	29.055us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.950s	42.380us	1	1	100.00
		keymgr_csr_aliasing	4.850s	641.898us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.910s	128.965us	1	1	100.00
V2	sideload	keymgr_sideload	24.450s	1.827ms	1	1	100.00
		keymgr_sideload_kmac	18.240s	1.697ms	1	1	100.00
		keymgr_sideload_aes	3.690s	174.627us	1	1	100.00
		keymgr_sideload_otbn	1.570s	60.205us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.540s	138.072us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.640s	58.339us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.390s	450.361us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.040s	174.697us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.350s	202.092us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.400s	31.100us	1	1	100.00
V2	stress_all	keymgr_stress_all	16.340s	510.832us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.880s	10.200us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.720s	82.224us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.440s	177.758us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.440s	177.758us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.990s	85.527us	1	1	100.00
		keymgr_csr_rw	0.950s	42.380us	1	1	100.00
		keymgr_csr_aliasing	4.850s	641.898us	1	1	100.00
		keymgr_same_csr_outstanding	1.190s	23.069us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.990s	85.527us	1	1	100.00
		keymgr_csr_rw	0.950s	42.380us	1	1	100.00
		keymgr_csr_aliasing	4.850s	641.898us	1	1	100.00
		keymgr_same_csr_outstanding	1.190s	23.069us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
		keymgr_tl_intg_err	3.240s	349.591us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	1.970s	115.226us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	1.970s	115.226us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	1.970s	115.226us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	1.970s	115.226us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.670s	289.411us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.240s	349.591us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	1.970s	115.226us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.910s	128.965us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.890s	148.152us	1	1	100.00
		keymgr_csr_rw	0.950s	42.380us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.890s	148.152us	1	1	100.00
		keymgr_csr_rw	0.950s	42.380us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.890s	148.152us	1	1	100.00
		keymgr_csr_rw	0.950s	42.380us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.640s	58.339us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.350s	202.092us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.350s	202.092us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.890s	148.152us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.240s	223.351us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.150s	40.790us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.640s	58.339us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.150s	40.790us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.150s	40.790us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.150s	40.790us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.800s	1.499ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.150s	40.790us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	18.840s	6.773ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	30	100.00