KMAC/MASKED Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.780s	672.237us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.030s	25.636us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.990s	16.812us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.760s	1.129ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.150s	140.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	70.226us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.990s	16.812us	1	1	100.00
		kmac_csr_aliasing	3.150s	140.624us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.890s	15.719us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	157.444us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	28.536m	179.366ms	1	1	100.00
V2	burst_write	kmac_burst_write	13.100s	191.660us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.166m	251.050ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.700m	160.123ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.072m	13.970ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.720s	596.477us	1	1	100.00
		kmac_test_vectors_shake_128	28.389m	84.504ms	1	1	100.00
		kmac_test_vectors_shake_256	1.441m	15.850ms	1	1	100.00
		kmac_test_vectors_kmac	1.940s	70.303us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.400s	53.456us	1	1	100.00
V2	sideload	kmac_sideload	3.677m	4.008ms	1	1	100.00
V2	app	kmac_app	4.040m	46.942ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.455m	5.349ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.564m	45.094ms	1	1	100.00
V2	error	kmac_error	4.414m	10.876ms	1	1	100.00
V2	key_error	kmac_key_error	6.380s	824.101us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.640s	349.292us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	27.760s	1.444ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.420s	115.479us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	40.910s	5.618ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.240s	53.730us	1	1	100.00
V2	stress_all	kmac_stress_all	7.193m	84.449ms	0	1	0.00
V2	intr_test	kmac_intr_test	0.790s	22.823us	1	1	100.00
V2	alert_test	kmac_alert_test	1.390s	53.426us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.880s	87.392us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.880s	87.392us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.030s	25.636us	1	1	100.00
		kmac_csr_rw	0.990s	16.812us	1	1	100.00
		kmac_csr_aliasing	3.150s	140.624us	1	1	100.00
		kmac_same_csr_outstanding	1.490s	58.183us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.030s	25.636us	1	1	100.00
		kmac_csr_rw	0.990s	16.812us	1	1	100.00
		kmac_csr_aliasing	3.150s	140.624us	1	1	100.00
		kmac_same_csr_outstanding	1.490s	58.183us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.650s	58.183us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.650s	58.183us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.650s	58.183us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.650s	58.183us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.470s	107.913us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.341m	17.094ms	1	1	100.00
		kmac_tl_intg_err	2.680s	119.693us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.680s	119.693us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.240s	53.730us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.780s	672.237us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.677m	4.008ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.650s	58.183us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.341m	17.094ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.341m	17.094ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.341m	17.094ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.780s	672.237us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.240s	53.730us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.341m	17.094ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.017m	11.142ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.780s	672.237us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.750s	3.082ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_stress_all has 1 failures.

    • 0.kmac_stress_all.45922323039287252796131852471163914395721987818460073531807102539217858471248
      Line 201, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log

        UVM_ERROR @ 84449341735 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 84449341735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---