KMAC/UNMASKED Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	23.890s	3.038ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	25.055us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.100s	131.538us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.100s	4.007ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.960s	544.980us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.370s	78.287us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.100s	131.538us	1	1	100.00
		kmac_csr_aliasing	6.960s	544.980us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.900s	13.720us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	70.539us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	7.299m	13.587ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.024m	17.263ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.188m	272.313ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.169m	88.094ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.515m	109.195ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.390s	4.817ms	1	1	100.00
		kmac_test_vectors_shake_128	1.667m	4.539ms	1	1	100.00
		kmac_test_vectors_shake_256	19.634m	73.228ms	1	1	100.00
		kmac_test_vectors_kmac	2.520s	138.510us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.020s	212.979us	1	1	100.00
V2	sideload	kmac_sideload	1.870m	5.356ms	1	1	100.00
V2	app	kmac_app	35.950s	2.555ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.198m	8.266ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.983m	24.285ms	1	1	100.00
V2	error	kmac_error	2.893m	3.294ms	1	1	100.00
V2	key_error	kmac_key_error	14.870s	30.882ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.130s	56.166us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	10.340s	161.356us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.910s	1.403ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	19.860s	9.274ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.390s	70.295us	1	1	100.00
V2	stress_all	kmac_stress_all	13.846m	48.049ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.960s	24.545us	1	1	100.00
V2	alert_test	kmac_alert_test	0.970s	22.807us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.130s	200.378us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.130s	200.378us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	25.055us	1	1	100.00
		kmac_csr_rw	1.100s	131.538us	1	1	100.00
		kmac_csr_aliasing	6.960s	544.980us	1	1	100.00
		kmac_same_csr_outstanding	1.560s	63.750us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	25.055us	1	1	100.00
		kmac_csr_rw	1.100s	131.538us	1	1	100.00
		kmac_csr_aliasing	6.960s	544.980us	1	1	100.00
		kmac_same_csr_outstanding	1.560s	63.750us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	214.952us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	214.952us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	214.952us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	214.952us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.740s	232.089us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	19.570s	1.864ms	1	1	100.00
		kmac_tl_intg_err	1.960s	93.571us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.960s	93.571us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.390s	70.295us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	23.890s	3.038ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.870m	5.356ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	214.952us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.570s	1.864ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.570s	1.864ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.570s	1.864ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	23.890s	3.038ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.390s	70.295us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.570s	1.864ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	22.330s	544.184us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	23.890s	3.038ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	26.240s	1.525ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.31427693404393218464509081576333217345832219754882593186403788385524698664593
      Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1524949724 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1524949724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---