OTBN Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 7.000s 141.802us 0 1 0.00
V1 single_binary otbn_single 6.000s 57.366us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 65.917us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 18.819us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 218.188us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 22.802us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 5.000s 300.770us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 18.819us 1 1 100.00
otbn_csr_aliasing 3.000s 22.802us 1 1 100.00
V1 mem_walk otbn_mem_walk 16.000s 184.455us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 946.733us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 21.000s 185.207us 0 1 0.00
V2 multi_error otbn_multi_err 48.000s 151.485us 0 1 0.00
V2 back_to_back otbn_multi 50.000s 381.230us 0 1 0.00
V2 stress_all otbn_stress_all 27.000s 143.464us 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 45.450us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 22.469us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 25.493us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 43.589us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 69.237us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 4.000s 294.574us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 4.000s 294.574us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 65.917us 1 1 100.00
otbn_csr_rw 3.000s 18.819us 1 1 100.00
otbn_csr_aliasing 3.000s 22.802us 1 1 100.00
otbn_same_csr_outstanding 5.000s 20.710us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 65.917us 1 1 100.00
otbn_csr_rw 3.000s 18.819us 1 1 100.00
otbn_csr_aliasing 3.000s 22.802us 1 1 100.00
otbn_same_csr_outstanding 5.000s 20.710us 1 1 100.00
V2 TOTAL 4 11 36.36
V2S mem_integrity otbn_imem_err 9.000s 29.667us 1 1 100.00
otbn_dmem_err 7.000s 40.698us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 7.000s 238.527us 0 1 0.00
otbn_controller_ispr_rdata_err 4.000s 16.208us 0 1 0.00
otbn_mac_bignum_acc_err 9.000s 42.845us 0 1 0.00
otbn_urnd_err 9.000s 43.493us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 27.206us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 14.310us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 82.906us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 3.000s 3.124us 0 1 0.00
otbn_tl_intg_err 9.000s 321.629us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 19.000s 205.819us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S prim_count_check otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 7.000s 141.802us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 7.000s 40.698us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 29.667us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 9.000s 321.629us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 45.450us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 29.667us 1 1 100.00
otbn_dmem_err 7.000s 40.698us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 22.469us 0 1 0.00
otbn_illegal_mem_acc 6.000s 27.206us 1 1 100.00
otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 29.667us 1 1 100.00
otbn_dmem_err 7.000s 40.698us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 22.469us 0 1 0.00
otbn_illegal_mem_acc 6.000s 27.206us 1 1 100.00
otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 45.450us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 29.667us 1 1 100.00
otbn_dmem_err 7.000s 40.698us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 22.469us 0 1 0.00
otbn_illegal_mem_acc 6.000s 27.206us 1 1 100.00
otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 36.469us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 41.816us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 15.000s 47.471us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 15.000s 47.471us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 44.250us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 7.000s 135.475us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 56.887us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 56.887us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 3.000s 25.540us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 50.000s 381.230us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 18.601us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 6.000s 57.366us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.000s 3.124us 0 1 0.00
V2S TOTAL 9 20 45.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.150m 1.807ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 41 48.78

Failure Buckets