PATTGEN Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	169.720us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	32.474us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	21.796us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	69.570us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	22.816us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	113.568us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	21.796us	1	1	100.00
		pattgen_csr_aliasing	1.000s	22.816us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	33.000s	1.402ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	8.000s	913.397us	1	1	100.00
V2	error	pattgen_error	2.000s	37.887us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.000s	32.112us	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	13.142us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	20.585us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	93.243us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	93.243us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	32.474us	1	1	100.00
		pattgen_csr_rw	1.000s	21.796us	1	1	100.00
		pattgen_csr_aliasing	1.000s	22.816us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	17.976us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	32.474us	1	1	100.00
		pattgen_csr_rw	1.000s	21.796us	1	1	100.00
		pattgen_csr_aliasing	1.000s	22.816us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	17.976us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	186.242us	1	1	100.00
		pattgen_sec_cm	2.000s	236.713us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	186.242us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	42.000s	15.698ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	74.991us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.34710102043913491793899510388709141029832748853917090355436462476103241689343
      Line 209, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4282253702 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 4282267350 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4282267350 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/10
        UVM_INFO @ 4282477878 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]