ROM_CTRL/64KB Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.700s	716.565us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.230s	747.662us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.790s	216.840us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.150s	524.811us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.330s	212.390us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.290s	1.677ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.790s	216.840us	1	1	100.00
		rom_ctrl_csr_aliasing	6.330s	212.390us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.350s	392.019us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.630s	702.397us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.690s	771.442us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	31.140s	5.936ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.120s	394.332us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	6.680s	727.333us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.320s	4.982ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.320s	4.982ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.230s	747.662us	1	1	100.00
		rom_ctrl_csr_rw	6.790s	216.840us	1	1	100.00
		rom_ctrl_csr_aliasing	6.330s	212.390us	1	1	100.00
		rom_ctrl_same_csr_outstanding	9.750s	303.921us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.230s	747.662us	1	1	100.00
		rom_ctrl_csr_rw	6.790s	216.840us	1	1	100.00
		rom_ctrl_csr_aliasing	6.330s	212.390us	1	1	100.00
		rom_ctrl_same_csr_outstanding	9.750s	303.921us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	34.640s	1.091ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.986m	2.006ms	0	1	0.00
		rom_ctrl_tl_intg_err	1.626m	448.717us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.986m	2.006ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.986m	2.006ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.986m	2.006ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.986m	2.006ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.700s	716.565us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.700s	716.565us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.700s	716.565us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.626m	448.717us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
		rom_ctrl_kmac_err_chk	13.120s	394.332us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.777m	9.307ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	34.640s	1.091ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.986m	2.006ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.705m	4.020ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.17441316529150644012932278069297022999571727914561054664078219785444118571723
      Line 426, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 135742508ps failed at 135742508ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 135778222ps failed at 135778222ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'