cf33148| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.830s | 240.137us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.570s | 50.343us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.730s | 26.632us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.170s | 193.825us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.680s | 18.694us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.220s | 289.984us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.730s | 26.632us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.680s | 18.694us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.660s | 298.572us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.550s | 980.693us | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 6.642m | 598.990ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 6.642m | 598.990ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 0.860s | 252.688us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.560s | 16.399us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.820s | 32.328us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.360s | 254.695us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.360s | 254.695us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.570s | 50.343us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 26.632us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.680s | 18.694us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.110s | 147.561us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.570s | 50.343us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 26.632us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.680s | 18.694us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.110s | 147.561us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.890s | 65.764us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.700s | 631.439us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.700s | 631.439us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.970s | 428.651us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.680s | 177.418us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 25.830s | 6.918ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.1420686472307115718722795695059989317087779899514979272667535811200079695470
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 428650774 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x51ea2104) == 0x1
UVM_INFO @ 428650774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.13951450456343766040988572436286094907996179747403969797424027203947163359223
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 298572016 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe6e7f04) == 0x1
UVM_INFO @ 298572016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.12030033550399814228434460243737885414339845069427992050801239034191113316202
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 177417527 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 177417527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---