SPI_DEVICE/1R1W Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	20.420s	11.684ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.970s	119.661us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.890s	381.383us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.690s	1.897ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.070s	1.204ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.620s	149.041us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.890s	381.383us	1	1	100.00
		spi_device_csr_aliasing	16.070s	1.204ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	15.833us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.160s	192.227us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.800s	85.849us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.710s	7.348us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.670s	6.006us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.200s	43.209us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.200s	43.209us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.790s	1.294ms	1	1	100.00
		spi_device_tpm_sts_read	0.690s	18.094us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.480s	3.018ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.990s	1.255ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.370s	6.448ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.370s	6.448ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.730s	4.295ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.730s	4.295ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.730s	4.295ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.730s	4.295ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.730s	4.295ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.100s	473.834us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.700s	2.457ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.700s	2.457ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.700s	2.457ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	16.260s	3.001ms	1	1	100.00
		spi_device_read_buffer_direct	11.530s	5.324ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.700s	2.457ms	1	1	100.00
		spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.581m	21.564ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.220s	101.473us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.220s	101.473us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	20.420s	11.684ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.040m	119.339ms	1	1	100.00
V2	stress_all	spi_device_stress_all	19.330s	1.594ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.810s	42.310us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.750s	11.302us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.610s	125.294us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.610s	125.294us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.970s	119.661us	1	1	100.00
		spi_device_csr_rw	1.890s	381.383us	1	1	100.00
		spi_device_csr_aliasing	16.070s	1.204ms	1	1	100.00
		spi_device_same_csr_outstanding	2.810s	114.507us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.970s	119.661us	1	1	100.00
		spi_device_csr_rw	1.890s	381.383us	1	1	100.00
		spi_device_csr_aliasing	16.070s	1.204ms	1	1	100.00
		spi_device_same_csr_outstanding	2.810s	114.507us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.270s	139.962us	1	1	100.00
		spi_device_tl_intg_err	12.920s	296.130us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.920s	296.130us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.317m	156.772ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.69542365612012196070652848373903583858157939313179702017027680611665878466831
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6062610 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[52])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6062610 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6062610 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[948])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.761003515482549432018236565503300781520031704151466241806136598856344830881
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3609668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd30539 [110100110000010100111001] vs 0x0 [0])
        UVM_ERROR @   3618668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb39e2c [101100111001111000101100] vs 0x0 [0])
        UVM_ERROR @   3640668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x99163a [100110010001011000111010] vs 0x0 [0])
        UVM_ERROR @   3740668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55de48 [10101011101111001001000] vs 0x0 [0])
        UVM_ERROR @   3745668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x32ef2a [1100101110111100101010] vs 0x0 [0])