SPI_DEVICE/2P Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.497m	220.771ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.150s	154.692us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.680s	84.241us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.820s	1.048ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.620s	610.164us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.500s	100.003us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.680s	84.241us	1	1	100.00
		spi_device_csr_aliasing	10.620s	610.164us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	30.026us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.800s	281.573us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.870s	22.724us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.060s	32.678us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	16.564us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.500s	197.578us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.500s	197.578us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	0.810s	19.986us	1	1	100.00
		spi_device_tpm_sts_read	0.720s	205.701us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.790s	89.613us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.860s	287.611us	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.820s	389.492us	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.820s	389.492us	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	12.140s	7.327ms	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	12.140s	7.327ms	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	12.140s	7.327ms	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	12.140s	7.327ms	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	12.140s	7.327ms	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.420s	1.194ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.360s	599.066us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.360s	599.066us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.360s	599.066us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.210s	356.816us	1	1	100.00
		spi_device_read_buffer_direct	2.380s	540.572us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.360s	599.066us	1	1	100.00
		spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	58.310s	21.036ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.700s	440.789us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.700s	440.789us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.497m	220.771ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	47.610s	3.594ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.811m	76.947ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.810s	21.489us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.730s	55.755us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.390s	48.497us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.390s	48.497us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.150s	154.692us	1	1	100.00
		spi_device_csr_rw	1.680s	84.241us	1	1	100.00
		spi_device_csr_aliasing	10.620s	610.164us	1	1	100.00
		spi_device_same_csr_outstanding	1.630s	27.044us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.150s	154.692us	1	1	100.00
		spi_device_csr_rw	1.680s	84.241us	1	1	100.00
		spi_device_csr_aliasing	10.620s	610.164us	1	1	100.00
		spi_device_same_csr_outstanding	1.630s	27.044us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.040s	70.245us	1	1	100.00
		spi_device_tl_intg_err	17.360s	3.263ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.360s	3.263ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	41.760s	35.507ms	1	1	100.00
		TOTAL			33	33	100.00