SPI_HOST Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.000s	5.107ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	23.899us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	19.512us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	209.932us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	91.220us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	201.530us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	19.512us	1	1	100.00
		spi_host_csr_aliasing	1.000s	91.220us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.263us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	41.235us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	38.019us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	169.687us	1	1	100.00
		spi_host_error_cmd	2.000s	85.620us	1	1	100.00
		spi_host_event	15.000s	6.878ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	45.019us	1	1	100.00
V2	speed	spi_host_speed	2.000s	45.019us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	45.019us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	57.733us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	24.517us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	45.019us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	45.019us	1	1	100.00
V2	duplex	spi_host_smoke	11.000s	5.107ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	11.000s	5.107ms	1	1	100.00
V2	stress_all	spi_host_stress_all	9.000s	1.502ms	1	1	100.00
V2	spien	spi_host_spien	10.000s	3.106ms	1	1	100.00
V2	stall	spi_host_status_stall	24.000s	4.040ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	365.679us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	169.687us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	134.522us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	47.468us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	341.564us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	341.564us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	23.899us	1	1	100.00
		spi_host_csr_rw	1.000s	19.512us	1	1	100.00
		spi_host_csr_aliasing	1.000s	91.220us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	169.733us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	23.899us	1	1	100.00
		spi_host_csr_rw	1.000s	19.512us	1	1	100.00
		spi_host_csr_aliasing	1.000s	91.220us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	169.733us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	65.500us	1	1	100.00
		spi_host_sec_cm	1.000s	45.607us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	65.500us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.117m	2.731ms	1	1	100.00
		TOTAL			26	26	100.00