SRAM_CTRL/MAIN Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	14.500s	2.039ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.820s	28.747us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.850s	16.805us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.420s	66.365us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	13.485us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.050s	353.242us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.850s	16.805us	1	1	100.00
		sram_ctrl_csr_aliasing	0.770s	13.485us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.919m	7.197ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.211m	19.614ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.864m	33.648ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.677m	11.575ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.453m	423.183ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.987m	6.208ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	31.810s	9.062ms	1	1	100.00
V2	executable	sram_ctrl_executable	39.270s	13.345ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	19.040s	1.576ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.236m	11.833ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.890s	2.710ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.610s	725.984us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.001m	919.530us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.930m	23.237ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.570s	4.212ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	44.989m	193.614ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.990s	15.131us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.430s	89.634us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.430s	89.634us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.820s	28.747us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	16.805us	1	1	100.00
		sram_ctrl_csr_aliasing	0.770s	13.485us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.970s	18.129us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.820s	28.747us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	16.805us	1	1	100.00
		sram_ctrl_csr_aliasing	0.770s	13.485us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.970s	18.129us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.390s	16.538ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.170s	34.030us	0	1	0.00
		sram_ctrl_tl_intg_err	2.890s	247.360us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.170s	34.030us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.890s	247.360us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.930m	23.237ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.930m	23.237ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.850s	16.805us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	39.270s	13.345ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	39.270s	13.345ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	39.270s	13.345ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	31.810s	9.062ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.360s	669.360us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.390s	16.538ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.250s	1.386ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	14.500s	2.039ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	14.500s	2.039ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	39.270s	13.345ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.170s	34.030us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	31.810s	9.062ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.170s	34.030us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.170s	34.030us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	14.500s	2.039ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.170s	34.030us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	30.430s	3.024ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.69511057438498052142407101368129292488381633649499194083825640401321517711217
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  34029983 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  34029983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---