SRAM_CTRL/RET Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	29.110s	260.910us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.650s	22.829us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	28.968us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.020s	150.065us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	23.188us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.810s	31.766us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	28.968us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	23.188us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.570s	4.389ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.420s	114.119us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.306m	22.424ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.235m	53.078ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	40.730s	3.396ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.622m	1.457ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.540s	848.994us	1	1	100.00
V2	executable	sram_ctrl_executable	1.173m	3.535ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.750s	1.977ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.463m	64.452ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.030s	245.869us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.970s	114.981us	1	1	100.00
		sram_ctrl_throughput_w_readback	38.160s	1.072ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.970m	84.068ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.690s	36.657us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	48.441m	31.320ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.650s	15.518us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.510s	68.779us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.510s	68.779us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.650s	22.829us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	28.968us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	23.188us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	28.187us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.650s	22.829us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	28.968us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	23.188us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	28.187us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.190s	484.308us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.660s	3.169us	0	1	0.00
		sram_ctrl_tl_intg_err	1.710s	2.602ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.660s	3.169us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.710s	2.602ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.970m	84.068ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.970m	84.068ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	28.968us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.173m	3.535ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.173m	3.535ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.173m	3.535ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.540s	848.994us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.020s	577.342us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.190s	484.308us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.750s	96.929us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	29.110s	260.910us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	29.110s	260.910us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.173m	3.535ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.660s	3.169us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.540s	848.994us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.660s	3.169us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.660s	3.169us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	29.110s	260.910us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.660s	3.169us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	25.210s	561.561us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.108255495452241124279823759848911875811706633829496249439368968148270420590639
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   3168670 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3168670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---