SYSRST_CTRL Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.670s 2.124ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 5.130s 2.486ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 1.920s 2.246ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.440s 2.350ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 9.130s 4.030ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.770s 2.088ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 21.040s 32.700ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.290s 2.696ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.770s 2.056ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.770s 2.088ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.290s 2.696ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 2.888m 127.163ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 25.780s 23.827ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 25.990s 26.278ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.540s 4.212ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 1.940s 2.527ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.710s 2.196ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 26.632m 776.063ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 5.450s 2.608ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 6.500s 11.349ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 15.130s 33.254ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 6.330s 9.224ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.850s 2.016ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.660s 2.022ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.140s 2.090ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.140s 2.090ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 9.130s 4.030ms 1 1 100.00
sysrst_ctrl_csr_rw 1.770s 2.088ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.290s 2.696ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.290s 5.232ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 9.130s 4.030ms 1 1 100.00
sysrst_ctrl_csr_rw 1.770s 2.088ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.290s 2.696ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.290s 5.232ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.188m 42.025ms 1 1 100.00
sysrst_ctrl_tl_intg_err 11.490s 22.507ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 11.490s 22.507ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.600s 4.162ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00