UART Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	12.290s	5.355ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.760s	14.793us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.590s	245.202us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.700s	57.318us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.890s	47.524us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.910s	22.410us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.590s	245.202us	1	1	100.00
		uart_csr_aliasing	0.890s	47.524us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	39.850s	63.030ms	1	1	100.00
V2	parity	uart_smoke	12.290s	5.355ms	1	1	100.00
		uart_tx_rx	39.850s	63.030ms	1	1	100.00
V2	parity_error	uart_intr	1.687m	347.485ms	1	1	100.00
		uart_rx_parity_err	14.770s	40.530ms	1	1	100.00
V2	watermark	uart_tx_rx	39.850s	63.030ms	1	1	100.00
		uart_intr	1.687m	347.485ms	1	1	100.00
V2	fifo_full	uart_fifo_full	29.700s	46.433ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.030m	113.418ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	38.080s	22.492ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.687m	347.485ms	1	1	100.00
V2	rx_break_err	uart_intr	1.687m	347.485ms	1	1	100.00
V2	rx_timeout	uart_intr	1.687m	347.485ms	1	1	100.00
V2	perf	uart_perf	6.148m	9.431ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.870s	2.364ms	1	1	100.00
V2	line_loopback	uart_loopback	10.870s	2.364ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	29.570s	25.212ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.170s	1.678ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.720s	1.149ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.850s	2.753ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.148m	136.131ms	1	1	100.00
V2	stress_all	uart_stress_all	16.120s	23.213ms	0	1	0.00
V2	alert_test	uart_alert_test	0.760s	39.050us	1	1	100.00
V2	intr_test	uart_intr_test	0.560s	103.819us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.490s	74.715us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.490s	74.715us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.760s	14.793us	1	1	100.00
		uart_csr_rw	0.590s	245.202us	1	1	100.00
		uart_csr_aliasing	0.890s	47.524us	1	1	100.00
		uart_same_csr_outstanding	0.750s	19.555us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.760s	14.793us	1	1	100.00
		uart_csr_rw	0.590s	245.202us	1	1	100.00
		uart_csr_aliasing	0.890s	47.524us	1	1	100.00
		uart_same_csr_outstanding	0.750s	19.555us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.120s	108.696us	1	1	100.00
		uart_tl_intg_err	1.050s	93.738us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.050s	93.738us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	34.020s	15.710ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	27	88.89

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 3 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.46182270942968195884414592701635850278980823138854987803488165143756103176419
      Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 17565126177 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 17565126177 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 18606826973 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (254 [0xfe] vs 252 [0xfc]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 18809985089 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 18809985089 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.64941398056132160592446933400514362424638880664708329900063012354953072438369
      Line 149, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9120259980 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 9120259980 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 9248819980 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/21
        UVM_INFO @ 9394899980 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/21
        UVM_INFO @ 9773819980 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/21
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.72643376790563814433119007663470164508853464236137339377206765020827250955254
      Line 86, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 17852357003 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 17947437875 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 18007355763 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 18016988339 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 18018294451 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0