CHIP Simulation Results

Monday October 20 2025 17:15:22 UTC

GitHub Revision: `cf33148`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.847m	3.439ms	1	1	100.00
		chip_sw_example_rom	1.065m	2.549ms	1	1	100.00
		chip_sw_example_manufacturer	2.338m	2.994ms	1	1	100.00
		chip_sw_example_concurrency	2.013m	2.759ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.355m	4.026ms	1	1	100.00
V1	csr_rw	chip_csr_rw	7.676m	6.001ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.036m	6.706ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	53.160m	30.980ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	47.660s	2.195ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	53.160m	30.980ms	1	1	100.00
		chip_csr_rw	7.676m	6.001ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	9.280s	226.922us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.439m	4.269ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.439m	4.269ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.439m	4.269ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.881m	3.939ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.881m	3.939ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.114m	4.402ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.039m	3.798ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.931m	4.059ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.553m	7.885ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.003m	8.656ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.277m	3.907ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.720m	4.984ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.720m	4.984ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.578m	2.671ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.322m	4.646ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.265m	2.816ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	16.552m	13.467ms	1	1	100.00
		chip_tap_straps_testunlock0	1.384m	2.461ms	1	1	100.00
		chip_tap_straps_rma	6.982m	6.939ms	1	1	100.00
		chip_tap_straps_prod	1.712m	3.007ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.373m	2.458ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.563m	8.947ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.800m	5.683ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.800m	5.683ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.210m	7.860ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	28.729m	17.796ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.285m	4.442ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.271m	6.011ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.575m	18.713ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.984m	3.022ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.829m	5.733ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.151m	3.222ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	26.788m	12.090ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.914m	2.952ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.747m	5.525ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.962m	2.407ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.593m	2.818ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	4.841m	6.418ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.502m	4.915ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.306m	2.333ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.502m	4.915ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.355m	3.136ms	1	1	100.00
		chip_sw_aes_smoketest	2.149m	3.441ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.072m	2.253ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.539m	2.630ms	1	1	100.00
		chip_sw_csrng_smoketest	2.752m	3.256ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.016m	6.664ms	1	1	100.00
		chip_sw_gpio_smoketest	3.300m	2.917ms	1	1	100.00
		chip_sw_hmac_smoketest	2.779m	2.936ms	1	1	100.00
		chip_sw_kmac_smoketest	3.062m	3.612ms	1	1	100.00
		chip_sw_otbn_smoketest	22.437m	10.957ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.656m	4.598ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.260m	6.350ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.438m	2.679ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.874m	2.967ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.428m	3.206ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.679m	2.124ms	1	1	100.00
		chip_sw_uart_smoketest	1.866m	2.553ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.238m	2.937ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	3.783m	3.312ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.187h	60.535ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.486m	14.760ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.213m	7.283ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.769m	3.078ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.037m	3.007ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.887h	54.060ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.062h	56.443ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.684m	3.003ms	1	1	100.00
V2	tl_d_illegal_access	chip_tl_errors	1.684m	3.003ms	1	1	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	53.160m	30.980ms	1	1	100.00
		chip_same_csr_outstanding	38.470m	27.072ms	1	1	100.00
		chip_csr_hw_reset	2.355m	4.026ms	1	1	100.00
		chip_csr_rw	7.676m	6.001ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	53.160m	30.980ms	1	1	100.00
		chip_same_csr_outstanding	38.470m	27.072ms	1	1	100.00
		chip_csr_hw_reset	2.355m	4.026ms	1	1	100.00
		chip_csr_rw	7.676m	6.001ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	39.840s	1.653ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.720s	47.186us	1	1	100.00
		xbar_smoke_large_delays	34.740s	5.651ms	1	1	100.00
		xbar_smoke_slow_rsp	42.950s	4.359ms	1	1	100.00
		xbar_random_zero_delays	28.040s	551.683us	1	1	100.00
		xbar_random_large_delays	1.090m	11.024ms	1	1	100.00
		xbar_random_slow_rsp	3.035m	20.338ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	13.370s	154.864us	1	1	100.00
		xbar_error_and_unmapped_addr	10.690s	333.229us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	25.230s	1.226ms	1	1	100.00
		xbar_error_and_unmapped_addr	10.690s	333.229us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.940s	15.510us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.407m	29.568ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	12.680s	354.219us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.955m	5.088ms	1	1	100.00
		xbar_stress_all_with_error	1.088m	3.196ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.044m	1.958ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.533m	683.851us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.486m	14.760ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	40.089m	28.286ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	44.128m	16.455ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.688m	11.384ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.483m	16.054ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.388m	16.663ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	44.664m	15.635ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.800m	15.195ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.330s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.880s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.120s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	19.000s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	19.010s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	19.130s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.230s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.620s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.070s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	20.800s	10.120us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.080s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.540s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.000s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.220s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.180s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.650s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.890s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.200s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.700s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.330s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.230s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.930s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.950s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.080s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.570s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.508m	10.945ms	1	1	100.00
		rom_e2e_asm_init_dev	42.948m	16.722ms	1	1	100.00
		rom_e2e_asm_init_prod	39.891m	15.526ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.050m	15.741ms	1	1	100.00
		rom_e2e_asm_init_rma	39.358m	15.111ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.842m	15.845ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.655m	14.443ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.117m	15.037ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.179m	15.470ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.381m	34.875ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.381m	34.875ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.139m	2.934ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.984m	3.022ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.629m	3.144ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.915m	3.278ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	26.408m	12.468ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.910m	3.264ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.256m	5.487ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.101m	5.731ms	1	1	100.00
		chip_plic_all_irqs_10	4.187m	3.485ms	1	1	100.00
		chip_plic_all_irqs_20	6.373m	4.368ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.791m	3.105ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	19.635m	13.759ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.820m	3.288ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.022m	2.658ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	24.152m	10.802ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.073m	6.841ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.042m	7.322ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.296h	254.826ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	2.902m	3.164ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.656m	4.598ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	2.902m	3.164ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.895m	8.391ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.895m	8.391ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.136m	7.313ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.241m	5.152ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.737m	6.224ms	1	1	100.00
		chip_sw_aes_idle	2.915m	3.278ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.532m	2.709ms	1	1	100.00
		chip_sw_kmac_idle	3.179m	2.973ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.069m	4.240ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.858m	4.977ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.400m	3.910ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.843m	4.871ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.378m	8.062ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.279m	4.626ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.500m	4.719ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.778m	4.365ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.393m	4.852ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.987m	3.230ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.773m	4.686ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.210m	7.860ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	6.238m	10.023ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.778m	4.365ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.393m	4.852ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.285m	4.442ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.271m	6.011ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.575m	18.713ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.984m	3.022ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.829m	5.733ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.151m	3.222ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	26.788m	12.090ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.914m	2.952ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.747m	5.525ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.962m	2.407ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.463m	2.554ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.338m	4.482ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.502m	7.288ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.656m	25.003ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.562m	3.248ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.213m	2.565ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.933m	8.638ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.289m	3.614ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.310m	5.293ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.267m	23.389ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	44.781m	24.186ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.210m	7.860ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	7.028m	4.918ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.220m	3.277ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	24.152m	10.802ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.163m	7.916ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	5.914m	4.735ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.598m	6.852ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.633m	2.762ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	25.242m	8.867ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.511m	2.548ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.698m	7.394ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.511m	2.548ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.163m	7.916ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.607m	2.461ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	24.533m	22.489ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.473m	5.377ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.271m	6.011ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.182m	4.194ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.285m	4.442ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.053h	43.290ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	24.533m	22.489ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.533m	3.894ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	29.535m	12.363ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.323m	5.010ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.053h	43.290ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.323m	5.010ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.323m	5.010ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.323m	5.010ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.323m	5.010ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.949m	14.680ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.682m	4.860ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.300m	4.583ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.300m	4.583ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.886m	3.187ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.151m	3.222ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.532m	2.709ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.486m	2.898ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.861m	3.378ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.723m	5.649ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.377m	5.024ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.211m	5.042ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.501m	4.338ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	29.535m	12.363ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	26.788m	12.090ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.612m	10.718ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	26.408m	12.468ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	44.043m	15.092ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.019m	2.988ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.990m	2.550ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.914m	2.952ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	29.535m	12.363ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.044m	3.229ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	21.202m	9.404ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.179m	2.973ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.256m	5.487ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	16.552m	13.467ms	1	1	100.00
		chip_tap_straps_rma	6.982m	6.939ms	1	1	100.00
		chip_tap_straps_prod	1.712m	3.007ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.269m	2.984ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.877m	6.355ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.323m	5.010ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.053h	43.290ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.525m	3.786ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.882m	6.149ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.450m	6.124ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.033m	6.351ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
		chip_sw_keymgr_key_derivation	29.535m	12.363ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.658m	9.772ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.756m	7.530ms	1	1	100.00
		chip_prim_tl_access	4.949m	14.680ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	6.238m	10.023ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.279m	4.626ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.500m	4.719ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.778m	4.365ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.393m	4.852ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.987m	3.230ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.773m	4.686ms	1	1	100.00
		chip_tap_straps_dev	16.552m	13.467ms	1	1	100.00
		chip_tap_straps_rma	6.982m	6.939ms	1	1	100.00
		chip_tap_straps_prod	1.712m	3.007ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.257m	10.712ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.674m	3.599ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.313m	3.406ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.595m	3.173ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.527m	2.894ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.469m	24.478ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.257m	10.712ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.106h	50.458ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	59.979m	48.506ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.781m	7.490ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.109h	47.247ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.469m	24.478ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.089m	2.299ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.029m	2.050ms	1	1	100.00
		rom_volatile_raw_unlock	59.630s	2.457ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.989m	17.238ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.575m	18.713ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.737m	6.224ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.737m	6.224ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.737m	6.224ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.720m	3.473ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	24.533m	22.489ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.720m	3.473ms	1	1	100.00
		chip_sw_keymgr_key_derivation	29.535m	12.363ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.309m	4.428ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.877m	2.340ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	24.533m	22.489ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.720m	3.473ms	1	1	100.00
		chip_sw_keymgr_key_derivation	29.535m	12.363ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.309m	4.428ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.877m	2.340ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.459m	4.895ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.269m	2.984ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.525m	3.786ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.882m	6.149ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.450m	6.124ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.033m	6.351ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.889m	7.076ms	1	1	100.00
		chip_prim_tl_access	4.949m	14.680ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.949m	14.680ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.687m	8.139ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.983m	6.360ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	22.393m	27.190ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.209m	7.210ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.596m	7.284ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.672m	6.889ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.798m	20.746ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.584m	16.182ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.895m	8.391ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.841m	13.394ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.908m	5.552ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.983m	6.360ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.523m	4.268ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	36.804m	34.794ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.481m	6.061ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.841m	4.686ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	30.195m	23.061ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.797m	6.668ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.706m	11.824ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	29.326m	30.333ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.566m	3.333ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.658m	9.772ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.658m	9.772ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.706m	11.824ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	30.195m	23.061ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.908m	5.552ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.656m	4.598ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.833m	4.186ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.861m	4.759ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.992m	4.133ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	19.635m	13.759ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.247m	3.120ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.073m	6.841ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.653m	4.410ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.917m	4.075ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.344m	2.942ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.877m	2.340ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.861m	4.759ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.861m	4.759ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	23.214m	21.779ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.042m	13.489ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.833m	4.186ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	6.272m	5.679ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.004m	5.866ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.982m	6.939ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.257m	10.712ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.101m	5.731ms	1	1	100.00
		chip_plic_all_irqs_10	4.187m	3.485ms	1	1	100.00
		chip_plic_all_irqs_20	6.373m	4.368ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.351m	2.945ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.840m	2.648ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.486m	14.760ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.313m	6.647ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.292m	2.840ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.673m	3.169ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.934m	3.367ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.309m	4.428ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.747m	5.525ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.399m	8.032ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.212m	7.544ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.756m	7.530ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.800m	5.683ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.797m	6.668ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.262m	23.371ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.138m	2.530ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.150m	3.037ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.901m	3.986ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.262m	23.371ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.262m	23.371ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	42.864m	21.040ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	42.864m	21.040ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.067m	6.205ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.381m	34.875ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.978m	2.276ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.090m	2.950ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.124m	3.698ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.660m	4.342ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.629m	8.201ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.511h	31.513ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	32.158m	12.316ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.315m	2.868ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.233m	2.964ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.714m	2.789ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.646h	71.478ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	7.903m	4.331ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.279m	11.460ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.479m	11.611ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.102m	12.714ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.205m	4.172ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.604m	4.307ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.949m	4.779ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.414s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.377m	5.462ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.551m	3.160ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.057m	7.422ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	11.005m	5.966ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.417m	2.369ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.333m	4.933ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.056m	2.576ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.110m	5.116ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.325m	5.477ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.341m	5.208ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.706m	11.824ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.279m	11.460ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.479m	11.611ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.102m	12.714ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.498m	4.890ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.681m	4.324ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.487h	38.301ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.487h	38.301ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.526m	3.450ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.881m	3.939ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.858m	18.575ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.639m	2.974ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.728m	4.428ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	35.117m	40.305ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.055m	2.927ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.325m	3.323ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.421m	3.638ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.365s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.595m	2.863ms	1	1	100.00
		TOTAL			283	326	86.81

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.55102076918797444717049168260173182485089958489030182739625544355501552393162
    Line 528, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.74041931054663507370131891266114042028309906298940673880313104354145106937829
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.43873636640971008047307202965830974909632152462218010576024570522482074727443
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.105782277746958693044704231924968288246223555854459537747757169998076932502291
    Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.61975929741175618307586305775381695691930576166793120738947690815629074188054
    Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.25494726708146849282243820648311083943424127095982868771967708488173440100829
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.14225883998121652510922872691402825045616014557460761184034331506845134994352
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1922038177663650601673033803384373170390877617337778885463142370219568778049
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.31750828699804439796278812498145963421519830413175710231787002898010671007148
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.39799011021626248289368810567648923254423606224788155989948007005608489033678
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.29749125843269592910221502266711439026953210338966130402056818492015401034299
    Line 528, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.93763652505370915869890156545718422603554592416107211852906882063556764246482
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.43844804927478180479780307594647130175172449841015087737211985789894209910382
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.54896024101474856775131276323410042951069702284020492090272193617801584816814
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.154s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.103351220431647137636834590946493703730057374256023259902295995753586256865099
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.34507497791979046315821521633275184601338299573159684964850652470477531669388
    Line 531, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.34074911591668521551228826830875071473184498268389948997567299079280010171472
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.48234262360980017682870020528261406282264401297284600459613715304643651565413
    Line 560, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.83195146519907679620880323101115377987661888621106824755543707362526188680771
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.59879847329571626397136823738527975228409004903270425005356878809174061420265
    Line 570, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2671.498500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2671.498500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.25069442534916328524594054894135407450184676345523620858026822308344560990299
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2840.291192 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2840.291192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.93146051257262517362544328054243059787765606925680493512560854846532964161089
    Line 424, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6351.107534 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6351.107534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.58631465890503581900333232701206182490136316359507021220837520956925671794440
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 40304.905641 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 40304.905641 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94930) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.111064260673005135659902300793571357870107515258239925803165825735927229649477
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4759.152375 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94930) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4759.152375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.19757183031242716289972341939309650316624148957379325148648392993265925953573
    Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34874.608317 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34874.608317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.17401138209672213393418325153492350035547313270694413608225124789318104160686
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3263.696914 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 52!
  UVM_INFO @ 3263.696914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.42179477556507929008171941110961416364190055048924952793522477293449449600078
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2658.194871 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2658.194871 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.77988933340985795559937923994757503220821095601675729606798428046210731557561
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.36114142269586560079325176033624296496467429986323135345925950246563908678797
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2898.153652 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2898.153652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.61942964482522510523511287497985309735811560097863720684769809862264846689318
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2789.335842 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2789.335842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.69202206133524013120646643774581538164919072270668757828527213125420432765216
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3078.392000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3078.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.30941772350054820261159304727317050329361398503383501468167840687425662497362
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3007.482500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3007.482500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.20405153712045888624266164178274311451955992848341706415731039611693887177038
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17795.801671 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17795.801671 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.52063248582084004489002687943929091057543210038530515660584119969793759403247
    Line 464, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4331.402869 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4331.402869 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.14129601786794694593327141223997726817780874958818547849226719285366679709902
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.115393864801771191064561782581137335222223405929439737590161180044168626649607
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33224) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.30698954068631041213446254603495396296168723735767491129721233428630707202023
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2195.230848 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33224) { a_addr: 'h106c4  a_data: 'hd0e395b2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h4  a_user: 'h18a32  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2195.230848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---