ADC_CTRL Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.790s	5.933ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.130s	863.562us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.200s	368.555us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.174m	45.168ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.680s	1.079ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.850s	465.840us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.200s	368.555us	1	1	100.00
		adc_ctrl_csr_aliasing	2.680s	1.079ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.856m	165.593ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.163m	325.344ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	14.488m	485.836ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	14.058m	493.361ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.916m	362.559ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.599m	205.270ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.508m	170.720ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.915m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	8.300s	3.783ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	21.820s	45.253ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.555m	88.215ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.850m	173.088ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.140s	436.727us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.000s	528.412us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.650s	498.972us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.650s	498.972us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.130s	863.562us	1	1	100.00
		adc_ctrl_csr_rw	1.200s	368.555us	1	1	100.00
		adc_ctrl_csr_aliasing	2.680s	1.079ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.130s	4.479ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.130s	863.562us	1	1	100.00
		adc_ctrl_csr_rw	1.200s	368.555us	1	1	100.00
		adc_ctrl_csr_aliasing	2.680s	1.079ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.130s	4.479ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.570s	4.635ms	1	1	100.00
		adc_ctrl_tl_intg_err	15.220s	8.228ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	15.220s	8.228ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	3.740s	2.119ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.4180324514326749183372275517822489128209189772452076980181412179142291696084
      Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---