HMAC Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 0.810s 164.065us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.200s 98.906us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.740s 22.355us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.760s 595.031us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.120s 1.202ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.220s 29.433us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.740s 22.355us 1 1 100.00
hmac_csr_aliasing 4.120s 1.202ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 48.370s 36.974ms 1 1 100.00
V2 back_pressure hmac_back_pressure 5.840s 150.517us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.569m 5.122ms 1 1 100.00
hmac_test_sha384_vectors 19.140s 515.028us 1 1 100.00
hmac_test_sha512_vectors 5.801m 11.535ms 1 1 100.00
hmac_test_hmac256_vectors 8.000s 266.419us 1 1 100.00
hmac_test_hmac384_vectors 7.830s 1.805ms 1 1 100.00
hmac_test_hmac512_vectors 9.700s 2.535ms 1 1 100.00
V2 burst_wr hmac_burst_wr 10.010s 1.086ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.848m 16.327ms 1 1 100.00
V2 error hmac_error 1.100m 53.846ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 14.620s 3.424ms 1 1 100.00
V2 save_and_restore hmac_smoke 0.810s 164.065us 1 1 100.00
hmac_long_msg 48.370s 36.974ms 1 1 100.00
hmac_back_pressure 5.840s 150.517us 1 1 100.00
hmac_datapath_stress 7.848m 16.327ms 1 1 100.00
hmac_burst_wr 10.010s 1.086ms 1 1 100.00
hmac_stress_all 2.577m 11.778ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 0.810s 164.065us 1 1 100.00
hmac_long_msg 48.370s 36.974ms 1 1 100.00
hmac_back_pressure 5.840s 150.517us 1 1 100.00
hmac_datapath_stress 7.848m 16.327ms 1 1 100.00
hmac_wipe_secret 14.620s 3.424ms 1 1 100.00
hmac_test_sha256_vectors 2.569m 5.122ms 1 1 100.00
hmac_test_sha384_vectors 19.140s 515.028us 1 1 100.00
hmac_test_sha512_vectors 5.801m 11.535ms 1 1 100.00
hmac_test_hmac256_vectors 8.000s 266.419us 1 1 100.00
hmac_test_hmac384_vectors 7.830s 1.805ms 1 1 100.00
hmac_test_hmac512_vectors 9.700s 2.535ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 0.810s 164.065us 1 1 100.00
hmac_long_msg 48.370s 36.974ms 1 1 100.00
hmac_back_pressure 5.840s 150.517us 1 1 100.00
hmac_datapath_stress 7.848m 16.327ms 1 1 100.00
hmac_burst_wr 10.010s 1.086ms 1 1 100.00
hmac_error 1.100m 53.846ms 1 1 100.00
hmac_wipe_secret 14.620s 3.424ms 1 1 100.00
hmac_test_sha256_vectors 2.569m 5.122ms 1 1 100.00
hmac_test_sha384_vectors 19.140s 515.028us 1 1 100.00
hmac_test_sha512_vectors 5.801m 11.535ms 1 1 100.00
hmac_test_hmac256_vectors 8.000s 266.419us 1 1 100.00
hmac_test_hmac384_vectors 7.830s 1.805ms 1 1 100.00
hmac_test_hmac512_vectors 9.700s 2.535ms 1 1 100.00
hmac_stress_all 2.577m 11.778ms 1 1 100.00
V2 stress_all hmac_stress_all 2.577m 11.778ms 1 1 100.00
V2 alert_test hmac_alert_test 0.760s 11.788us 1 1 100.00
V2 intr_test hmac_intr_test 0.750s 13.536us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.520s 222.350us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.520s 222.350us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.200s 98.906us 1 1 100.00
hmac_csr_rw 0.740s 22.355us 1 1 100.00
hmac_csr_aliasing 4.120s 1.202ms 1 1 100.00
hmac_same_csr_outstanding 1.660s 187.894us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.200s 98.906us 1 1 100.00
hmac_csr_rw 0.740s 22.355us 1 1 100.00
hmac_csr_aliasing 4.120s 1.202ms 1 1 100.00
hmac_same_csr_outstanding 1.660s 187.894us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.950s 79.614us 1 1 100.00
hmac_tl_intg_err 1.600s 189.744us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.600s 189.744us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 0.810s 164.065us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.770s 253.696us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 15.380s 1.201ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.010s 325.004us 1 1 100.00
TOTAL 28 28 100.00