I2C Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.900s	2.684ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	6.360s	3.928ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.810s	41.947us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.720s	16.344us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.620s	368.487us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.110s	412.142us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.070s	38.413us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.720s	16.344us	1	1	100.00
		i2c_csr_aliasing	1.110s	412.142us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.220s	74.149us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.830s	15.528us	0	1	0.00
V2	host_maxperf	i2c_host_perf	7.281m	70.145ms	1	1	100.00
V2	host_override	i2c_host_override	0.870s	16.254us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	41.830s	3.352ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	46.900s	11.026ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.230s	103.356us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.470s	282.503us	1	1	100.00
		i2c_host_fifo_reset_rx	3.020s	331.045us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.673m	3.694ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.250s	962.680us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.210s	493.970us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.720s	2.146ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	7.229m	33.218ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.160s	747.259us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.430s	2.141ms	1	1	100.00
		i2c_target_intr_smoke	7.770s	1.309ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.020s	289.695us	1	1	100.00
		i2c_target_fifo_reset_tx	1.930s	270.304us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	37.200s	44.564ms	1	1	100.00
		i2c_target_stress_rd	16.430s	2.141ms	1	1	100.00
		i2c_target_intr_stress_wr	1.637m	24.217ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.880s	6.351ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.716m	3.029ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.030s	741.099us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	17.610s	10.101ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.130s	423.684us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.870s	198.962us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	7.281m	70.145ms	1	1	100.00
		i2c_host_perf_precise	1.360s	70.504us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.250s	962.680us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.050s	366.680us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.040s	541.770us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.030s	442.607us	1	1	100.00
		i2c_target_nack_txstretch	1.190s	594.162us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.070s	1.587ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.910s	3.104ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.660s	37.750us	1	1	100.00
V2	intr_test	i2c_intr_test	1.000s	16.437us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.440s	573.010us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.440s	573.010us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.810s	41.947us	1	1	100.00
		i2c_csr_rw	0.720s	16.344us	1	1	100.00
		i2c_csr_aliasing	1.110s	412.142us	1	1	100.00
		i2c_same_csr_outstanding	0.870s	78.381us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.810s	41.947us	1	1	100.00
		i2c_csr_rw	0.720s	16.344us	1	1	100.00
		i2c_csr_aliasing	1.110s	412.142us	1	1	100.00
		i2c_same_csr_outstanding	0.870s	78.381us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.380s	82.165us	1	1	100.00
		i2c_sec_cm	0.790s	41.196us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.380s	82.165us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.570s	177.505us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.860s	22.042us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.610s	9.220ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.108262750018349106527114036110036559951440054051840920394608848951708718416323
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  74149452 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  74149452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.114027161685963573364233235548092573705506121275248807141365451199332810655470
      Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @  15528380 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  15528380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.102622525427276132968214841180905178152970298758579515453075628337933449273618
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 177505442 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 177505442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.11842655664017346120498033638136780817667230812620399901953032618312356330764
      Line 105, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9220058090 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9220058090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.87510615167472156049060238728896975868879176907613733592885404848058825281612
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2146178079 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2146178079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.68064430853687262890798968030149009796374101965670238600736552726996322521623
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  22041782 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 91 [0x5b])
        UVM_INFO @  22041782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.83694385643499400716212291842504401510260595470416448476785736426493403938813
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10101316652 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10101316652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.11542967635733292523404507814399444929723511164004286382542077202904209868600
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 594162425 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 594162425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---