| V1 |
smoke |
kmac_smoke |
7.790s |
474.160us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.980s |
30.657us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.130s |
206.495us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
10.680s |
1.177ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
7.610s |
486.337us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.300s |
75.997us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.130s |
206.495us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.610s |
486.337us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.880s |
12.712us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.300s |
36.642us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
9.397m |
14.401ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
6.289m |
19.459ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
34.750s |
9.571ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.572m |
59.516ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.986m |
29.848ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
16.420s |
1.660ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.259m |
26.456ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
23.035m |
35.393ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.150s |
84.923us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.630s |
120.199us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
2.790m |
9.580ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
4.624m |
23.955ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
16.730s |
3.169ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
22.560s |
4.843ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
58.220s |
25.769ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
1.810s |
734.869us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
1.260s |
75.630us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.440s |
45.929us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.020s |
14.875us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
17.150s |
8.592ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.440s |
72.691us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
4.540m |
212.988ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.940s |
142.452us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.940s |
14.847us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.510s |
1.349ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.510s |
1.349ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.980s |
30.657us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.130s |
206.495us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.610s |
486.337us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.240s |
26.876us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.980s |
30.657us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.130s |
206.495us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.610s |
486.337us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.240s |
26.876us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.780s |
211.532us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.780s |
211.532us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.780s |
211.532us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.780s |
211.532us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.220s |
1.260ms |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
37.940s |
16.279ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
1.760s |
190.197us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
1.760s |
190.197us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.440s |
72.691us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
7.790s |
474.160us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
2.790m |
9.580ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.780s |
211.532us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
37.940s |
16.279ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
37.940s |
16.279ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
37.940s |
16.279ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
7.790s |
474.160us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.440s |
72.691us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
37.940s |
16.279ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
5.030m |
13.649ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
7.790s |
474.160us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.073m |
6.650ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |