KMAC/UNMASKED Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	8.190s	415.166us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.990s	22.130us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.040s	54.387us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.610s	1.007ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.370s	390.410us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.840s	69.685us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.040s	54.387us	1	1	100.00
		kmac_csr_aliasing	7.370s	390.410us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.780s	12.522us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.040s	89.782us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.179m	85.558ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.627m	2.266ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.147m	91.886ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.485m	77.971ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.140s	1.631ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.290s	7.256ms	1	1	100.00
		kmac_test_vectors_shake_128	35.043m	424.364ms	1	1	100.00
		kmac_test_vectors_shake_256	1.594m	7.329ms	1	1	100.00
		kmac_test_vectors_kmac	2.110s	137.599us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.880s	395.986us	1	1	100.00
V2	sideload	kmac_sideload	40.320s	2.957ms	1	1	100.00
V2	app	kmac_app	25.480s	3.406ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.904m	106.478ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.602m	13.669ms	1	1	100.00
V2	error	kmac_error	2.741m	2.878ms	1	1	100.00
V2	key_error	kmac_key_error	2.350s	1.234ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	48.880s	10.183ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	7.380s	116.736us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.530s	5.262ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	24.600s	4.830ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	10.650s	1.084ms	1	1	100.00
V2	stress_all	kmac_stress_all	21.442m	152.896ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.700s	21.754us	1	1	100.00
V2	alert_test	kmac_alert_test	1.070s	21.399us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.680s	112.106us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.680s	112.106us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.990s	22.130us	1	1	100.00
		kmac_csr_rw	1.040s	54.387us	1	1	100.00
		kmac_csr_aliasing	7.370s	390.410us	1	1	100.00
		kmac_same_csr_outstanding	1.870s	178.825us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.990s	22.130us	1	1	100.00
		kmac_csr_rw	1.040s	54.387us	1	1	100.00
		kmac_csr_aliasing	7.370s	390.410us	1	1	100.00
		kmac_same_csr_outstanding	1.870s	178.825us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.300s	221.813us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.300s	221.813us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.300s	221.813us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.300s	221.813us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.840s	821.423us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.730s	3.826ms	1	1	100.00
		kmac_tl_intg_err	2.270s	508.040us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.270s	508.040us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	10.650s	1.084ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	8.190s	415.166us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	40.320s	2.957ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.300s	221.813us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.730s	3.826ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.730s	3.826ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.730s	3.826ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	8.190s	415.166us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	10.650s	1.084ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.730s	3.826ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.720m	12.141ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	8.190s	415.166us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.203m	17.599ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.10526184352269234830206627974266303142773244971126006930697408587015673524640
      Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10183116465 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb95f000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
        UVM_INFO @ 10183116465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.26537478268816185872879561035481205305571015333086757850505923999293532198921
      Line 198, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17598944044 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17598944044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---