PATTGEN Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	309.919us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	14.798us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	10.566us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	127.027us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	46.656us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	28.351us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	10.566us	1	1	100.00
		pattgen_csr_aliasing	2.000s	46.656us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	10.000s	2.691ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	34.000s	2.748ms	1	1	100.00
V2	error	pattgen_error	1.000s	62.894us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.000s	53.349us	0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	40.688us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	15.085us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	750.075us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	750.075us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	14.798us	1	1	100.00
		pattgen_csr_rw	2.000s	10.566us	1	1	100.00
		pattgen_csr_aliasing	2.000s	46.656us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	46.310us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	14.798us	1	1	100.00
		pattgen_csr_rw	2.000s	10.566us	1	1	100.00
		pattgen_csr_aliasing	2.000s	46.656us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	46.310us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	180.779us	1	1	100.00
		pattgen_sec_cm	1.000s	67.398us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	180.779us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	11.000s	5.576ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	44.183us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.105517120205174178389965768004302118569674807720741982942084216706571127447040
      Line 111, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 926720569 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 926726735 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 926726735 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 927143405 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.72505772671492155600252192249199815830493925538472195540605948518916825561793
      Line 129, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @  53348967 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10109