RV_TIMER Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.260s	546.513us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.780s	14.321us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	35.587us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.190s	38.184us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.970s	74.014us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.850s	30.674us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	35.587us	1	1	100.00
		rv_timer_csr_aliasing	0.970s	74.014us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.010s	98.942us	1	1	100.00
V2	disabled	rv_timer_disabled	1.650s	1.127ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.270s	10.484ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.270s	10.484ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.710s	6.970ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.630s	12.344us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.740s	17.800us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.220s	26.509us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.220s	26.509us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.780s	14.321us	1	1	100.00
		rv_timer_csr_rw	0.610s	35.587us	1	1	100.00
		rv_timer_csr_aliasing	0.970s	74.014us	1	1	100.00
		rv_timer_same_csr_outstanding	0.740s	140.221us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.780s	14.321us	1	1	100.00
		rv_timer_csr_rw	0.610s	35.587us	1	1	100.00
		rv_timer_csr_aliasing	0.970s	74.014us	1	1	100.00
		rv_timer_same_csr_outstanding	0.740s	140.221us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	91.432us	1	1	100.00
		rv_timer_tl_intg_err	1.160s	507.852us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.160s	507.852us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.590s	39.212us	1	1	100.00
V3	max_value	rv_timer_max	0.900s	180.708us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	9.760s	3.273ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.34957505876731970633212430967937825774876060311807654616168415816075066210289
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 180707805 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 180707805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---