SPI_DEVICE/1R1W Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.203m	59.609ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.830s	15.812us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.570s	86.416us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.670s	749.386us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.080s	1.135ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.370s	57.789us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.570s	86.416us	1	1	100.00
		spi_device_csr_aliasing	15.080s	1.135ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	14.103us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.110s	56.129us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.860s	13.439us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.790s	1.985us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.700s	3.476us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.940s	54.071us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.940s	54.071us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.930s	10.092ms	1	1	100.00
		spi_device_tpm_sts_read	0.800s	61.189us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.570s	1.675ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.170s	863.997us	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.900s	594.753us	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.900s	594.753us	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.200s	3.127ms	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.200s	3.127ms	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.200s	3.127ms	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.200s	3.127ms	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.200s	3.127ms	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.000s	510.408us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.780s	798.513us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.780s	798.513us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.780s	798.513us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	11.080s	5.255ms	1	1	100.00
		spi_device_read_buffer_direct	2.550s	132.183us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.780s	798.513us	1	1	100.00
		spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	26.350s	5.366ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.980s	152.992us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.980s	152.992us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.203m	59.609ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.280s	1.622ms	1	1	100.00
V2	stress_all	spi_device_stress_all	42.440s	5.606ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.870s	14.882us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.670s	12.941us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.710s	197.893us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.710s	197.893us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.830s	15.812us	1	1	100.00
		spi_device_csr_rw	1.570s	86.416us	1	1	100.00
		spi_device_csr_aliasing	15.080s	1.135ms	1	1	100.00
		spi_device_same_csr_outstanding	2.840s	529.081us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.830s	15.812us	1	1	100.00
		spi_device_csr_rw	1.570s	86.416us	1	1	100.00
		spi_device_csr_aliasing	15.080s	1.135ms	1	1	100.00
		spi_device_same_csr_outstanding	2.840s	529.081us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.130s	43.052us	1	1	100.00
		spi_device_tl_intg_err	9.580s	1.072ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.580s	1.072ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.822m	22.212ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.52611479365403624074411471923445389914175062773532114037748431795101547548028
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1304180 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1304180 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1304180 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.85160377101316567874533767780261991539845691354822381128004588790300907029335
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    945907 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x378489 [1101111000010010001001] vs 0x0 [0])
        UVM_ERROR @   1018907 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc205cb [110000100000010111001011] vs 0x0 [0])
        UVM_ERROR @   1086907 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3bfa4f [1110111111101001001111] vs 0x0 [0])
        UVM_ERROR @   1116907 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x535446 [10100110101010001000110] vs 0x0 [0])
        UVM_ERROR @   1153907 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3152f2 [1100010101001011110010] vs 0x0 [0])