SPI_DEVICE/2P Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 1.850m 80.921ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.290s 40.911us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.070s 339.696us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 15.360s 1.254ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 10.220s 427.819us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.920s 563.493us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.070s 339.696us 1 1 100.00
spi_device_csr_aliasing 10.220s 427.819us 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.660s 17.980us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.790s 69.499us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 0.840s 28.787us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.020s 32.057us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 0.700s 20.258us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.010s 50.189us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.010s 50.189us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 2.820s 2.159ms 1 1 100.00
spi_device_tpm_sts_read 0.850s 62.733us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 7.030s 3.516ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 3.190s 838.691us 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 2.660s 273.237us 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 2.660s 273.237us 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 cmd_read_status spi_device_intercept 8.180s 3.472ms 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 8.180s 3.472ms 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 8.180s 3.472ms 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 cmd_fast_read spi_device_intercept 8.180s 3.472ms 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 8.180s 3.472ms 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 flash_cmd_upload spi_device_upload 16.600s 15.543ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 17.280s 14.458ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 17.280s 14.458ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 17.280s 14.458ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 10.070s 2.723ms 1 1 100.00
spi_device_read_buffer_direct 3.300s 445.239us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 17.280s 14.458ms 1 1 100.00
spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 quad_spi spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 dual_spi spi_device_flash_all 0.910s 24.725us 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 2.940s 446.986us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 2.940s 446.986us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 1.850m 80.921ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 17.280s 3.404ms 1 1 100.00
V2 stress_all spi_device_stress_all 3.214m 104.398ms 1 1 100.00
V2 alert_test spi_device_alert_test 0.690s 23.845us 1 1 100.00
V2 intr_test spi_device_intr_test 0.870s 37.507us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 1.970s 312.997us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 1.970s 312.997us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.290s 40.911us 1 1 100.00
spi_device_csr_rw 2.070s 339.696us 1 1 100.00
spi_device_csr_aliasing 10.220s 427.819us 1 1 100.00
spi_device_same_csr_outstanding 2.170s 105.421us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.290s 40.911us 1 1 100.00
spi_device_csr_rw 2.070s 339.696us 1 1 100.00
spi_device_csr_aliasing 10.220s 427.819us 1 1 100.00
spi_device_same_csr_outstanding 2.170s 105.421us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.310s 989.435us 1 1 100.00
spi_device_tl_intg_err 15.960s 3.675ms 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 15.960s 3.675ms 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 1.111m 7.576ms 1 1 100.00
TOTAL 33 33 100.00