SRAM_CTRL/MAIN Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.300s	4.961ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.850s	46.359us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.810s	89.056us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.930s	567.226us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.910s	28.740us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.980s	361.113us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.810s	89.056us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	28.740us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.511m	7.895ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.497m	6.866ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.926m	7.275ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.228m	77.191ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	20.514m	24.679ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.739m	49.063ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	45.570s	11.614ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.422m	10.557ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	50.750s	998.797us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.752m	9.676ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	25.490s	768.741us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.880s	5.186ms	1	1	100.00
		sram_ctrl_throughput_w_readback	15.940s	798.484us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.461m	16.454ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.230s	342.671us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	54.423m	367.845ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.900s	25.139us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.850s	90.307us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.850s	90.307us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.850s	46.359us	1	1	100.00
		sram_ctrl_csr_rw	0.810s	89.056us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	28.740us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	85.332us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.850s	46.359us	1	1	100.00
		sram_ctrl_csr_rw	0.810s	89.056us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	28.740us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	85.332us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	21.710s	15.406ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.870s	4.477us	0	1	0.00
		sram_ctrl_tl_intg_err	1.260s	336.062us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.870s	4.477us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.260s	336.062us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.461m	16.454ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.461m	16.454ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.810s	89.056us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.422m	10.557ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.422m	10.557ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.422m	10.557ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	45.570s	11.614ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.940s	684.091us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	21.710s	15.406ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.410s	3.509ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.300s	4.961ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.300s	4.961ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.422m	10.557ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.870s	4.477us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	45.570s	11.614ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.870s	4.477us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.870s	4.477us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.300s	4.961ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.870s	4.477us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	27.470s	1.564ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.20167685966028614669711927835347118407920637033569709388156283940826151049867
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4476758 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4476758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---