SRAM_CTRL/RET Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	18.980s	592.571us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	13.607us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.600s	53.628us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.550s	225.129us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	66.141us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.330s	117.987us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.600s	53.628us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	66.141us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.550s	362.586us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.890s	163.800us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.200s	1.360ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.240m	3.696ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	28.180s	6.500ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.927m	3.873ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.680s	1.474ms	1	1	100.00
V2	executable	sram_ctrl_executable	57.100s	2.743ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.040s	1.218ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.112m	27.553ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	29.080s	122.399us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.810s	267.190us	1	1	100.00
		sram_ctrl_throughput_w_readback	5.050s	347.082us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.386m	23.323ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.690s	280.827us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	44.270m	278.801ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.640s	13.630us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.350s	496.523us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.350s	496.523us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	13.607us	1	1	100.00
		sram_ctrl_csr_rw	0.600s	53.628us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	66.141us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	17.282us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	13.607us	1	1	100.00
		sram_ctrl_csr_rw	0.600s	53.628us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	66.141us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	17.282us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.600s	1.528ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.610s	2.050us	0	1	0.00
		sram_ctrl_tl_intg_err	1.930s	697.653us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.610s	2.050us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.930s	697.653us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.386m	23.323ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.386m	23.323ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.600s	53.628us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	57.100s	2.743ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	57.100s	2.743ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	57.100s	2.743ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.680s	1.474ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.760s	39.586us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.600s	1.528ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.710s	92.549us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	18.980s	592.571us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	18.980s	592.571us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	57.100s	2.743ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.610s	2.050us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.680s	1.474ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.610s	2.050us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.610s	2.050us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	18.980s	592.571us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.610s	2.050us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.155m	1.616ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.20585927366746503224234085229201270365791537227458772910933461913471346805125
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  92549372 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x20)
        UVM_INFO @  92549372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.61823603379593200136586086459158667950255489810161285040977895673151363261957
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2050181 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2050181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---