UART Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.130s	5.344ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.770s	15.671us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.780s	53.357us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.450s	130.041us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.850s	32.938us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.710s	57.833us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.780s	53.357us	1	1	100.00
		uart_csr_aliasing	0.850s	32.938us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	30.480s	58.018ms	1	1	100.00
V2	parity	uart_smoke	7.130s	5.344ms	1	1	100.00
		uart_tx_rx	30.480s	58.018ms	1	1	100.00
V2	parity_error	uart_intr	4.710s	11.165ms	1	1	100.00
		uart_rx_parity_err	2.641m	166.682ms	1	1	100.00
V2	watermark	uart_tx_rx	30.480s	58.018ms	1	1	100.00
		uart_intr	4.710s	11.165ms	1	1	100.00
V2	fifo_full	uart_fifo_full	10.950s	39.486ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.846m	144.011ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	4.816m	263.309ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.710s	11.165ms	1	1	100.00
V2	rx_break_err	uart_intr	4.710s	11.165ms	1	1	100.00
V2	rx_timeout	uart_intr	4.710s	11.165ms	1	1	100.00
V2	perf	uart_perf	5.634m	8.366ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.670s	2.178ms	1	1	100.00
V2	line_loopback	uart_loopback	3.670s	2.178ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.183m	64.308ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	8.260s	26.400ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.630s	2.908ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	1.230s	1.277ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.274m	224.290ms	1	1	100.00
V2	stress_all	uart_stress_all	3.738m	126.587ms	0	1	0.00
V2	alert_test	uart_alert_test	0.720s	44.206us	1	1	100.00
V2	intr_test	uart_intr_test	0.800s	14.367us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.730s	103.698us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.730s	103.698us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.770s	15.671us	1	1	100.00
		uart_csr_rw	0.780s	53.357us	1	1	100.00
		uart_csr_aliasing	0.850s	32.938us	1	1	100.00
		uart_same_csr_outstanding	0.700s	488.174us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.770s	15.671us	1	1	100.00
		uart_csr_rw	0.780s	53.357us	1	1	100.00
		uart_csr_aliasing	0.850s	32.938us	1	1	100.00
		uart_same_csr_outstanding	0.700s	488.174us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.960s	46.423us	1	1	100.00
		uart_tl_intg_err	1.020s	201.261us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.020s	201.261us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	30.430s	8.961ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.114886948921283219914897615012492480951507330946712984046971643869740498468653
      Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 64285400058 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64285834848 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64286269638 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64286704428 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64287139218 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.100494569722327900460649161785995792515543602308224209183354896693925299523825
      Line 102, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 126537383586 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 126538363170 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 126539342754 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 126540322338 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 126542281506 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0